Desk-top electronic computer with MOS circuit logic

• US 3,939,452 A
• Filed: 07/11/1973
• Issued: 02/17/1976
• Est. Priority Date: 07/14/1972
• Status: Expired due to Term

• Current Assignee: Ing. C. Olivetti & C., SpA (Telecom Italia S.p.A.)
• Original Assignee: Ing. C. Olivetti & C., SpA (Telecom Italia S.p.A.)
• Inventors: Faggian, Gian Franco
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Thomas, James D.
• Application Number:
  US05/378,354
• Time in Patent Office: 951 Days
• Field of Search: 340/172.5, 235/156
• US Class Current: 712/32
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/22 Means for limiting or controlling the pin/gate ratio
• CPC Class Codes: G06F 15/7835 on more than one IC chip

Abstract

A desk-top electronic computer with MOS circuit logic comprising an input device, an output device and a logic unit adapted to carry out the various operations of the computer. The logic unit is disposed on at least two MOS circuit chips synchronized by a main oscillator. Each MOS chip is provided with a corresponding timing circuit adapted to generate mutually coordinated timing signals. The logic unit includes a read only memory or ROM for storing the microinstructions commanding the various functions, a computing unit and a control unit adapted to permit the selection of the microinstructions from the ROM by addressed access for the purpose of supplying a sequence of microinstructions to the computing unit, access of the address and output of the microinstructions taking place through a single connection between the ROM and the control unit.

Claims

1. In a desk-top electronic computer disposed on at least three semiconductor chips:

input-output means disposed on at least the first of the three semiconductor chips for receiving data signals applied thereto and for feeding data signals therefrom to the remaining semiconductor chips;

processing means receptive of data signals fed from said input-output means for processing the data signals, said processing means including arithmetic means disposed on the second semiconductor chip and receptive of data signals from said input-output means for performing arithmetic operations thereon, a memory instruction register and a memory address register both disposed on the first semiconductor chip, control means disposed on the third semiconductor chip and receptive of data signals from said input-output means for controlling the arithmetic means to perform selected arithmetic operations and comprising a read-only memory having addressable microinstructions stored therein and circuit means disposed on the three semiconductor chips for transferring over a first single signal conductor between the three semiconductor chips both the data signals from the memory address register to address the read-only memory and the data signals of the addressed microinstruction from the read-only memory to the memory instruction register; and

timing means disposed on the three semiconductor chips and interconnected by a second single signal conductor for synchronizing the data signal flow on the three semiconductor chips.

2. A desk-top electronic computer according to claim 1, wherein said processing means comprises a plurality of registers each having a plurality of cells for storing different characters and disposed on said second chip and wherein said timing means comprises a first pair of counters disposed on said first chip and including a character counter developing signals defining character time periods for identifying the various characters in said cells of said registers and a bit weight counter developing signals defining bit weight time periods for each character time period for identifying the various bits for each character in said cells.

3. A desk-top computer according to claim 2, wherein said timing means further comprises a second pair of counters disposed on said second chip and wherein said one pair of counters comprises self synchronizing circuit means for identifying a starting state of said first pair of counters upon the starting of the computer, and means for applying one character signal on said second single signal conductor to define a synchronizing time period and wherein said second pair of counters has means receptive of the character signal over said second single signal conductor for synchronizing the count therein to the character signal.

4. A desk-top computer according to claim 2, wherein said timing means has means defining two clock signals, wherein said registers have means receptive of the two clock signals for shifting said registers and wherein said bit weight counter has means receptive of said two clock signals for enabling same to count and wherein said character counter is responsive to one output line of said bit weight counter for enabling same to count.

5. A desk-top computer according to claim 4, wherein said timing means comprises a second pair of character and bit weight counters each including shift registers and wherein the bit weight counter of said second pair of counters has means receptive of said two clock signals for shifting same and the character counter of said second pair of counters has means receptive of another shift signal developed by the bit weight counter of said second pair of counters, a synchronizing circuit for identifying a first state of the shift register of said first pair of counters, a decoder circuit coactive with said first pair of counters to define a synchronizing time period applied to said second single signal conductor to connect the first pair of counters to the shift register of said second pair of counters for synchronizing said second pair of counters therewith.

6. A desk-top electronic computer according to claim 2, wherein said processing means comprises an increasing circuit connected to said address register for selecting in each timing cycle a new successive address and an address varying circuit for selectively varying the address stored in said address register for selecting a memory address different from that to be selected by said increasing circuit, said address varying circuit comprising means for varying a portion of said address for selecting a new address within a given partial address range of said read-only memory and means for completely replacing said address with a new address for selecting any address within the full address range of said read-only memory.

7. A computer according to claim 1, wherein said processing means comprises, a plurality of accumulating registers receptive of data signals to be processed, a circuit responsive to a given microinstruction for shifting the data of at least one accumulating register in one direction, a two-character auxiliary register connected to the one accumulating register and means responsive to a given microinstruction and the data in said two-character register to cause the shifting of the data in the opposite direction to said one direction.

8. A computer according to claim 1, wherein said timing means has means defining timing cycles and wherein said processing means comprises accumulating registers each receptive of data to be processed, counting means for counting each timing cycle from 0 to a predetermined number in response to a given microinstruction, and comparison means receptive of the output of said counting means and the output of said character counter to identify in each cycle the cell of the accumulating register being operated on.

9. A computer according to claim 8, comprising a decimal point register for storing the coded position of the decimal point, a first comparator receptive of the data from said counting means and the data of the decimal point register for comparing the two and a second comparator receptive of the complement of the data of said decimal point register and the data from said counting means for comparing the two.

10. A computer according to claim 1, wherein said circuit means comprises a first gate for enabling a memory address to pass through said first single signal conductor during a first period of time and a second gate for enabling a microinstruction to pass through said first single signal conductor during a second period of time.