Apparatus for locating faults in a working storage

• US 3,940,601 A
• Filed: 08/30/1974
• Issued: 02/24/1976
• Est. Priority Date: 09/05/1973
• Status: Expired due to Term

• Current Assignee: Gilles Jean Marcel Bottard, Michel Henry
• Original Assignee: Gilles Jean Marcel Bottard, Michel Henry
• Inventors: Henry, Michel, Bottard, Gilles Jean Marcel
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/502,165
• Time in Patent Office: 543 Days
• Field of Search: 235/153 AC, 340/172.5
• US Class Current: 714/735
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

The disclosure describes a device for locating faults in a working storage arranged in rows and columns.

The device includes an auxiliary storage which holds a sequence of test words and means for cyclically writing the test words into the working storage and reading the test words out of the working storage. A bit for bit word comparator compares the words read out of the working storage with the words read into the working storage and detects bits of the words which do not match in order to identify defective components. First and second registers record the row and the column to which the defective component belongs.

Claims

1. In a data processing system including a working storage consisting essentially in a plurality of identical components each having several selectively addressable store cells at which at least one bit of a data can be stored, said components being arranged in a matrix array wherein each column constitutes a block capable of storing several data words at respective addresses and wherein each row corresponds to at least one and the same bit position of said words, said working storage being further provided with circuit means operative for selectively writing or reading a data word at any predetermined address of any one of said blocks, a method for locating faults in said working storage, which comprises the preliminary step of determining a sequence of at least three test words each having as many bits as a data word and between which both logic states are distributed so that each bit presents each state at least once in said sequence, and which further comprises the operating steps of:

-- writing repetitively said sequence of test words at successive addresses of a first one of said blocks until all addresses thereof are filled, then reading out successively the content of each address of said first block and comparing same to that test word previously written at the said address, and whether any corresponding bits thereof differ, determining the position of said differing bits and registering the row of the involved defective component;

-- then repeating for said first block the aforesaid operating step with cyclic permutation of said test words in said sequence up to their initial ranking, to thereby register the rows of every defective components in said first block, and further registering together the relevant column;

-- and thereafter repeating the aforesaid steps for each block of said working storage, to thereby list every defective component thereof, each one being identified by the row and column to which it pertains.

2. Method according to claim 1, wherein the number of said test words in said sequence differs from any power of 2 smaller than the number of addresses of a component or block.

3. Method according to claim 1, comprising the additional step of:

-- writing a neutral word at all addresses of every blocks of said working storage other that under test, said neutral word having as many bits as a data word, which are all in the same logic state.

4. Method according to claim 1, comprising the supplementary step of identifying any faulty aforesaid circuit means of said working storage, from a consideration of the distribution of said defective components thereof as listed involving at least one full row and/or column of said matrix array, or the whole array.

5. In a data processing system including a working storage consisting essentially in a plurality of identical components each having several selectively addressable store cells at which at least one bit of data can be stored, said components being arranged in a matrix array wherein each column constitute a block capable of storing several data words at respective addresses and wherein each row corresponds to at least one and the same bit position of said words, said working storage being further provided with addressing circuits operatively connected to all aforesaid components of said matrix array for enabling a determined address thereof, with validating circuits operatively and respectively connected to all aforesaid components pertaining to a same column for enabling the corresponding block, with data in and data out circuits operatively and respectively connected to all aforesaid components pertaining to a same row for writing and reading data at the relevant bit positions, and with write/read selection circuits operatively connected to all aforesaid components for controlling selective writing or reading of a data word at the enabled address of the enabled block, an apparatus for detecting faults in said working storage, which comprises:

-- an auxiliary storage containing a sequence of at least three test words each having as many bits as a data word and between which both logic states are distributed so that each bit presents each state at least once in said sequence, and auxiliary means associated thereto for cyclically reading out said sequence from any specified test word thereof, said auxiliary means being operatively connected to said data in circuits of said working storage;

-- comparison means having two sets of inputs respectively connected to said data out circuits of said working storage and to said auxiliary means, said comparison means being operative for comparing each bit of the content read out at a determined address of said working storage with the corresponding bit of that test word previously written at the said address, and for producing an output signal identifying the position of any differing bits;

-- row registering means operatively coupled to said comparison means to receive said output signal and to register the row of the involved defective component of said working storage;

-- column registering means operatively coupled to said block validating circuits of said working storage through gate means operated by said row registering means to register the column of said defective component;

-- localization means operatively coupled to said row and column registering means for listing every defective components of said working storage;

-- and control means for coordinating the operation of said working storage, auxiliary storage and aforesaid means, so that every addresses of every blocks of said working storage are successively tested with every test words of said auxiliary storage.

6. Apparatus according to claim 5, wherein said auxiliary storage is a permanent storage.

7. Apparatus according to claim 5, wherein said control means consists in a control unit of said data processing system provided with a special subroutine program for testing said working storage.

8. Apparatus according to claim 5, wherein said control means consists in a special control generator or microprocessor supplying a special subroutine program, possibly under control of timing signals from said data processing system.