Method for providing reconfigurable microelectronic circuit devices and products produced thereby

• US 3,940,740 A
• Filed: 06/27/1973
• Issued: 02/24/1976
• Est. Priority Date: 06/27/1973
• Status: Expired due to Term

• Current Assignee: Actron Industries Inc (The Boeing Co.)
• Original Assignee: Actron Industries Inc (The Boeing Co.)
• Inventors: Coontz, Leland I.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US05/374,242
• Time in Patent Office: 972 Days
• Field of Search: 340/166 R, 340/173 R, 340/173 AM, 29/574, 29/577, 29/576, 29/575, 317/234 M, 317/235 AJ, 235/153
• US Class Current: 438/130
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The utility of microelectronic devices and the yield of a microelectronic fabricating process is increased by providing, in addition to the desired circuits, "redundant" circuits of the same type. Each circuit has included, in at least one access lead, a nonvolatile, electrically alterable semiconductor device, which can be "set" to either conduct or not conduct power to the circuit.

During testing, only the desired number of devices are rendered accessible by "setting" the semiconductor device to conduct.

A microelectronic device having repetitive rows and/or columns for memory cells or logical processors is provided with additional rows and columns. An electrically alterable device is placed in each row and column. Upon the successful test of each row, the row enabling device is set to a conductive state. Any row containing a defective device is not enabled. If additional defects exist, and no redundant rows are available, redundant columns are disabled to isolate the defective devices.

Claims

1. Method of improving the yield of batch processed, microcircuit memory arrays comprising the steps of:

a. forming on a unitary substrate a microcircuit array of a predetermined number of rows and columns of selection conductors intersecting at memory devices with an electrically alterable switching device in at least all rows;

b. forming on the same unitary substrate and at the same time the predetermined number of rows and columns are formed at least one additional row including memory devices at all intersections, and an electrically alterable switching device;

c. altering the associated row switching devices in succession to enable testing of the individual memory cells in each successive row and testing the individual memory cells in each successive row;

d. disabling those rows containing defective memory cells by realtering the associated row switching device to disable access to the memory cells of the row and, if access to less than the predetermined number of rows has been enabled;

e. repeating the testing step on the additional row,

whereby the additional row can be substituted for a defective row to achieve the predetermined number of rows of the memory array.

2. The method of calim 1, above, wherein:

a. the forming steps include forming on the same unitary substrate and at the same time the predetermined number of rows and columns are formed, electrically alterable switching devices in all of the columns and the forming of at least one additional redundant column including an electrically alterable switching device in said column;

b. the testing step further includes the initial altering of the associated column switching devices to enable access to the columns; and

if, after the testing step is repeated, less than the predetermined number of rows remain enabled, the further steps of;

c. enabling one of the previously disabled rows; and

d. disabling the column in which the defective cell of the previously disabled row is found and enabling the additional redundant column,

whereby the additional, redundant row and column are employed to attempt to achieve an array of the predetermined number of rows and columns.

3. The method of claim 2, above, wherein the creating steps further include:

the forming on the same unitary substrate and at the same time the predetermined number of rows and columns are formed row and column addressing circuits connected to said rows and columns and wherein every row address line is connected to said redundant row through a separate, electrically alterable switching device and every column address line is connected to said redundant column through a separate, electrically alterable switching device; and

said disabling step includes the enabling of the address line switching device connecting the additional row or column to the address line of the disabled row or column,

whereby an enabled, additional row or column takes the address of a disabled row or column.

4. Method for improving yield of batch processed, microcircuits comprising the steps of:

a. forming redundant circuits simultaneously with the desired circuits and on the same unitary substrate;

b. forming electrically alterable switching devices in association with each of said desired and redundant circuits at the same time and on the same unitary substrate as the desired and redundant circuits;

c. testing said desired circuits for operability;

d. setting said switching devices to include only operating ones of said desired circuits;

e. testing said redundant circuits for operability; and

f. setting said switching devices to include additional ones of the operating, redundant circuits sufficient to provide a predetermined desired operating configuration.

5. The combination with an integrated microelectronic memory array including a predetermined plurality of row and column selection conductors having memory cells at each intersection, for improving the production yield thereof comprising:

a. a redundant, duplicate row conductor having memory cells located at the intersections with the plurality of column conductors, said redundant row formed on the same unitary substrate and at the same time as the microelectronic memory array;

b. an electrically alterable switching circuit fabricated in each of the plurality of row conductors and in said duplicate row conductor, for selectively enabling and disabling individual row conductors, said electrically alterable switching circuits formed on the same unitary substrate and at the same time as the microelectronic memory array; and

c. altering means, integral with the memory array, formed on the same unitary substrate and at the same time as the microelectronic memory array, for selectively enabling individual ones of said switching circuits for testing the memory cells in the row associated therewith and for disabling those rows containing defective memory cells, whereby said redundant row is available to be substituted for a row containing a defective memory cell in attempting to achieve a memory array having a predetermined plurality of operable rows.

6. The combination of claim 5, above, further including:

additional redundant duplicate row conductors having memory cells located at the intersections with the plurality of column conductors, said additional redundant duplicate row conductors formed on the same unitary substrate and at the same time as the microelectronic memory array;

electrically alterable switching circuits fabricated in each said additional redundant duplicate row conductor on the same unitary substrate and at the same time as the microelectronic memory array, for selectively enabling and disabling said additional row conductors; and

said altering means further including means for selectively enabling and disabling said electrically alterable switching circuits in said additional redundant duplicate row conductors for testing the memory cells in the row associated therewith and for disabling the rows containing defective cells.

7. The combination of claim 5, above, further including:

a redundant duplicate column conductor having memory cells at the intersections with all of said row conductors, said redundant column conductor formed on the same unitary substrate and at the same time as the microelectronic memory array;

an electrically alterable switching circuit fabricated on the same unitary substrate and at the same time as the microelectronic memory array in each of the plurality of column conductors and in said duplicate column conductors for selectively enabling and disabling individual conductors; and

wherein said altering means include means for selectively enabling and disabling individual ones of said column switching circuits for testing the memory cells in the columns associated therewith.

8. The combination of claim 7, above, further including:

additional redundant duplicate column conductors having memory cells at the intersections with row conductors, said additional redundant duplicate column conductors formed on the same unitary substrate and at the same time as the microelectronic memory array;

electrically alterable switching circuits formed on the same unitary substrate and at the same time as the microelectronic memory array in each said additional redundant duplicate column conductor for selectively enabling and disabling said column conductors; and

said altering means further include means for selectively enabling and disabling said electrically alterable switching circuits in said additional column conductors for testing the memory cells in the column associated therewith.

9. The combination of claim 8, above, further including:

additional redundant duplicate row conductors having memory cells located at the intersections with the plurality of column conductors, said additional redundant duplicate row conductors formed on the same unitary substrate and at the same time as the microelectronic memory array;

electrically alterable switching circuits fabricated in each said additional redundant duplicate row conductor on the same unitary substrate and at the same time as the microelectronic memory array, for selectively enabling and disabling said additional row conductors; and

said altering means further including means for selectively enabling and disabling said electrically alterable switching circuits in said additional redundant duplicate row conductors for testing the memory cells in the row associated therewith and for disabling the rows containing defective cells.

10. Method for repairing a batch processed microcircuit array wafer having thereon desired circuits in a predetermined operating configuration, each of the circuits having a plurality of electrically alterable switching devices associated therewith which are settable to enable or disable the corresponding circuits, said method comprising the steps of:

a. testing the desired circuits for operability;

b. setting the switching devices to include only operating ones of said desired circuits; and

c. repeating said testing and setting steps to include additional ones of the operating redundant circuits sufficient to provide the predetermined desired operating configuration.

11. Method for reconfiguring to an alternate operating configuration a batch processed microcircuit array wafer having thereon a plurality of desired circuits in a predetermined operating configuration and having alternate circuits corresponding to selected ones of the desired circuits, each of the selected and alternate circuits having electrically alterable switching devices associated therewith which are settable to enable or disable the corresponding circuit, said method comprising the steps of:

a. setting the switching devices associated with one of the selected circuits to disable that selected circuit in the predetermined operating configuration;

b. setting the switching devices associated with the corresponding alternate circuit to enable the corresponding alternate circuit in the alternate operating configuration; and

c. repeating the said setting steps with the associated switching circuits of each of the remaining selected circuits and corresponding alternate circuits until the microcircuit array is reconfigured from the predetermined operating configuration to the alternate operating configuration.