Interconnecting unit for independently operable data processing systems

• US 3,940,743 A
• Filed: 11/05/1973
• Issued: 02/24/1976
• Est. Priority Date: 11/05/1973
• Status: Expired due to Term

• Current Assignee: Digital Equipment Corporation (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Fitzgerald, Brian P.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Woods, Paul R.
• Application Number:
  US05/412,572
• Time in Patent Office: 841 Days
• Field of Search: 340/172.5
• US Class Current: 710/305
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

A unit for interconnecting otherwise independently operable data processing systems. When one data processing system addresses the interconnecting unit, the unit acts like a peripheral device. It converts the address to a physical memory address for the other data processing system. Furthermore it interrupts the other system to effect a data transfer either to or from the other system.

Claims

1. In a data processing system including first and second buses for transferring data, address and control signals, means with a plurality of first storage locations connected to said first bus, each of said first storage locations being identified by an address on said first bus, means connected to said first bus for generating addresses including addresses for said first storage locations and other addresses, means for transmitting onto said first bus first transfer control signals for effecting a data transfer over said first bus, and means with a plurality of second storage locations connected to said second bus, each of said second storage locations being identified by an address on said second bus, the improvement of interconnecting means connected to said first and second buses comprising:

A. a bidirectional data path for coupling data signals between the first and second buses,

B. decoding means responsive to preselected ones of the other addresses on said first bus for enabling said interconnecting means,

C. means responsive to the receipt of one of the preselected addresses in said decoding means for converting an address on the first bus to an address on said second bus corresponding to one of said second storage locations,

D. means responsive to the first transfer control signals on the first bus for transferring data between said first bus and said bidirectional data path, and

E. means for generating second transfer control signals in response to the address and first transfer control signals, said data processing system additionally including means responsive to second transfer control signals on said second bus for transferring signals between said second bus and the second addressed location identified by the address from said address conversion means to thereby transfer the data between said bidirectional data path and said one of said second storage locations.

2. A data processing system as recited in claim 1 wherein said bidirectional data path additionally comprises

i. a storage register for receiving data from said first bus, and

ii. means responsive to the first transfer control signals and said decoding means for enabling said storage register to store data.

3. A data processing system as recited in claim 1 wherein the address signals include first and second groups of signals, said decoding means being responsive to the first group of signals and said address conversion means additionally comprising means for storing a substitute group of address signals and means for concatenating the substitute group of address signals with the second group of address signals to thereby identify one of said second storage locations.

4. A data processing system as recited in claim 3 wherein said data processing system additionally includes means connected to the second bus for generating addresses for said second storage locations and means for transmitting onto the second bus second transfer control signals and wherein said storage means for the substitute group of address signals is one of the addressed second storage locations, said system additionally comprising means connected to said second bus for altering the contents of said storage means for the substitute group of address signals in response to the address and second transfer control signals.

5. A data processing system as recited in claim 1 wherein said second transfer control signal generating means includes:

i. means for transmitting onto the second bus an interrupting request signal in response to the receipt of a preselected address in said decoder means, said data processing system additionally including means responsive to the receipt of an interrupting request signal on the second bus for performing an interruption operation, and

ii. means for generating signals for effecting a transfer of data during the interruption operation.

6. A unit for connection to a data processing system including first and second independently operable digital computer systems, each digital computer system including a set of physical locations identified by memory addresses and connected to a bus including address, control and data signal paths and means for effecting a transfer between locations on the bus, said unit interconnecting the first and second digital computer systems and said unit comprising:

A. a first channel responsive to one of a preselected plurality of memory addresses other than addresses for physical locations in the first digital computer system for effecting a data transfer between the first system bus as an originating bus and the bus in the second digital computer system as a target bus,

B. a second channel responsive to one of a preselected plurality of memory addresses other than addresses for physical locations in the second digital computer system for effecting a data transfer between the second system bus as an originating bus and the bus in the first digital computer system as a target bus,

C. each of said channels including;

i. an address decoder responsive to the receipt of address signals corresponding to the preselected plurality of memory addresses on its originating bus for selecting the channel,

ii. means connected to said address decoder for converting the address on the originating bus to an address for a physical location on the target bus in response to the receipt by said decoder of the address signals corresponding to the preselected plurality of memory addresses,

iii. first channel transfer means responsive to the transfer means in the digital computer system connected to the originating bus and enabled by said address decoder for transferring data between said channel and the originating bus, and

iv. second channel transfer means responsive to said address decoder for generating transfer control signals onto the target bus, the transfer means in the digital computer system connected to the target bus transferring data between the channel and the target bus in response to the transfer control signals.

7. An interconnecting unit as recited in claim 6 wherein said address signals include first and second groups of signals, each said address decoder being responsive to the first group of address signals on its originating bus, said address conversion means additionally including a relocation register for storing a substitute group of address signals to be substituted for the address signals in the first group to thereby define the physical location on the target bus.

8. An interconnecting unit as recited in claim 7 wherein said relocation register constitutes one of the physical locations connected to the target bus and the digital computer system connected to the target bus alters, the contents of said relocation register.

9. An interconnecting unit as recited in claim 6 wherein each digital computer system generates transfer control signals including signals indicating the direction of a data transfer, each channel additionally comprising a control buffer register for storing the direction signals from the originating bus and means for enabling said control buffer register when an address in the originating bus identifies said interconnecting unit.

10. An interconnecting unit as recited in claim 9 wherein said bidirectional data path in said channel comprises a data buffer register for receiving data from the originating bus in response to the first direction signals indicating a transfer of data to the target bus.

11. An interconnecting unit as recited in claim 10 wherein said bidirectional data path in the channel comprises a direct data path between the originating and target buses for receiving data from the target bus in response to other direction signals indicating a transfer of data to the originating bus.

12. An interconnecting unit as recited in claim 6 wherein each digital computer system includes means for generating onto the originating bus a master synchronization signal after address and transfer control signals are present on the originating bus, said first channel transfer means including means responsive to a master synchronization signal from the originating bus for generating a slave synchronization signal onto the originating bus upon the completion of a data transfer over the originating bus.

13. An interconnecting unit as recited in claim 12 wherein said second transfer means includes means responsive to said address decoder for transmitting onto the target bus an interruption request signal thereby to interrupt operations in the digital computer system connected to the target bus, means responsive to the granting of the interrupt request for transferring address signals from said converting means and transfer control signals onto the target bus and means for transmitting a delayed master synchronization signal onto the target bus, the digital computer system responding to the master synchronization signal by generating a slave synchronization signal upon the completion of a transfer over the target bus.

14. An interconnecting unit as recited in claim 6 wherein said interconnecting unit additionally comprises a status and control means for passing information between the first and second digital computer systems and wherein said status and control means includes:

i. a status register for each channel, each status register including a first bit position designating whether its corresponding channel has new data, and a second bit position designating whether the other channel has new data,

ii. control means for setting the second bit position when the first bit position is set, and

iii. means connected to the corresponding channel and responsive to the second bit position being set for generating an interrupting request signal to the corresponding system.

15. An interconnecting unit as recited in claim 14 wherein said status register additionally includes data bit positions, the contents of said first and second bit positions indicating whether new data is present in said data bit positions in the corresponding status registers.

16. An interconnecting unit as recited in claim 14 wherein said each of said channels additionally comprises a data buffer and wherein the first bit position in said status register indicates whether new data is present in the data buffer in the corresponding channel and the second bit position indicates whether new data in the data is present buffer of the other of said channels.

17. An interconnecting unit as recited in claim 14 wherein said status and control means includes:

i. first and second multi-bit status and control registers each constituting a physical location in their respective digital computer systems, said respective digital computer system being connected for altering the contents of predetermined bit positions, and

ii. an address decoder responsive to an address of said status and control register for enabling the corresponding register.

18. An interconnecting unit as recited in claim 17 wherein the contents of a first bit position in each of said status and control registers indicates whether an error condition exists and the contents of a second bit position indicates whether the corresponding digital computer system may be interrupted, said status and control circuit means additionally including means responsive to the contents of the first and second bit positions for generating interruption signals for the respective digital computer system.

19. An interconnecting unit as recited in claim 18 wherein certain bit positions in one of said status and control registers associated with one of said digital computer systems contain information about the status of the other digital computer system.