Programmable logic controller
First Claim
1. A programmable controller for operating a controlled system having a plurality of input and output devices the combination comprising:
- a random access memory which stores a set of instructions that comprise a control program, which stores a first set of status bits that comprise an input image table and that correspond to input devices on the controlled system, and which stores a second set of status bits that comprise an output image table and that correspond with output devices on the controlled system;
a processor connected directly to said random access memory and including means for continuously cycling said random access memory to execute said control program and to thereby update the status of said output image table in response to the status of said input image table;
interface circuitry connected to the input and output devices on said control system for converting signals from said input devices which are indicative of their status to corresponding logic level signals and for converting logic level signals to signals for driving said output devides to an indicated status; and
a scanner circuit connected directly to said random access memory and to said interface circuitry, said scanner circuit including means connected to said processor for interrupting the operation of said processor to steal a memory cycle, date input means operable during an interrupt to couple the status of selected input devices from said interface circuit to the input image table, and data output means operable during an interrupt to couple the status of selected bits in said output image table to the interface circuit for driving corresponding selected output devices on said controlled system, wherein the status bits which comprise said input and output image tables are stored in separately addressable lines in said random access memory, each of which lines contains a plurality of status bits, said scanner circuit includes an I/O address counter which addresses one line in said random access memory during each interrupt, and all the status bits in said addressed line are coupled with said interface circuit during the interrupt.
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Accused Products
Abstract
A programmable controller includes a processor which executes a control program to alter the state of an output image table stored in a read/write memory in response to the state of an input image table stored in the memory. An input/output scanner circuit connects directly to the read/write memory and periodically steals a memory cycle from the processor to couple the status of input and output devices with corresponding bits in the input and output image tables. The rate at which the scanner circuit operates is independent of the processor speed and is selected to accommodate the input/output interface circuitry on the programmable controller.
55 Citations
21 Claims
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1. A programmable controller for operating a controlled system having a plurality of input and output devices the combination comprising:
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a random access memory which stores a set of instructions that comprise a control program, which stores a first set of status bits that comprise an input image table and that correspond to input devices on the controlled system, and which stores a second set of status bits that comprise an output image table and that correspond with output devices on the controlled system; a processor connected directly to said random access memory and including means for continuously cycling said random access memory to execute said control program and to thereby update the status of said output image table in response to the status of said input image table; interface circuitry connected to the input and output devices on said control system for converting signals from said input devices which are indicative of their status to corresponding logic level signals and for converting logic level signals to signals for driving said output devides to an indicated status; and a scanner circuit connected directly to said random access memory and to said interface circuitry, said scanner circuit including means connected to said processor for interrupting the operation of said processor to steal a memory cycle, date input means operable during an interrupt to couple the status of selected input devices from said interface circuit to the input image table, and data output means operable during an interrupt to couple the status of selected bits in said output image table to the interface circuit for driving corresponding selected output devices on said controlled system, wherein the status bits which comprise said input and output image tables are stored in separately addressable lines in said random access memory, each of which lines contains a plurality of status bits, said scanner circuit includes an I/O address counter which addresses one line in said random access memory during each interrupt, and all the status bits in said addressed line are coupled with said interface circuit during the interrupt. - View Dependent Claims (2)
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3. In a programmable controller, the combination comprising:
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means for storing an input image table which stores the status of input devices connected to the programmable controller; means for storing an output image table which stores the status of output devices connected to the programmable controller; means for storing a control program containing a plurality of program instructions; a processor for sequentially and cyclically executing the program instructions, said processor including means connected to said input image table storage means for examining the status of selected bits stored therein in response to selected program instructions and including means connected to said output image table storage means for setting the status of selected bits stored therein in response to other selected program instructions; and a scanner circuit connected to said input and output image table storage means and said processor, said scanner circuit including means for periodically interrupting the operation of said processor, means for coupling the status of selected bits stored in said input image table storage means with input devices connected to said programmable controller during an interrupt, and means for coupling the status of selected bits stored in said output image table storage means with output devices connected to said programmable controller during an interrupt. - View Dependent Claims (4, 5, 6)
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7. A programmable controller, the combination comprising:
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a random access memory which stores a control program comprised of a plurality of program instructions, an input image table that contains a plurality of status bits which correspond to input devices connected to the programmable controller, and an output image table that contains a plurality of status bits that correspond to output devices connected to the programmable controller; a processor connected to said random access memory and including a program instruction counter for sequentially reading said program instructions out of said memory, means for examining the logic state of selected status bits in said input image table in response to selected program instructions read from said memory, and means for setting the logic state of selected status bits in said output image table in response to other selected program instructions read from said memory; and a scanner circuit connected to said random access memory and including I/O address counter means for selecting sets of status bits in said output image table and said input image table, said scanner circuit further including interrupt means connected to said processor for generating a request signal to said processor, said scanner circuit also including coupling means operable in response to a grant signal received from said processor to couple a selected set of status bits in said image tables with their corresponding input and output devices. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A programmable controller, the combination comprising:
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a random access memory which stores a control program comprised of a plurality of program instructions, an input image table that contains a plurality of status bits which correspond to input devices connected to the programmable controller, and an output image table that contains a plurality of status bits that correspond to output devices connected to the programmable controller; a processor connected to said random access memory and including a program instruction counter for sequentially reading said program instructions out of said memory, means for examining the logic state of a selected status bit in said input and output image tables in response to a selected program instruction read from said memory, and means for setting the logic state of a selected status bit in said output image table in response to another selected program instruction read from said memory; and a scanner circuit connected to said random access memory and said processor, said scanner circuit including I/O address counter means for selecting a set of status bits in said input and output image tables and for concurrently selecting the corresponding set of devices on the controlled system, said scanner circuit also including means for coupling said selected set of status bits between said input and output image tables and its corresponding set of devices. - View Dependent Claims (16, 17)
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18. A programmable controller for operating a controlled system, the combination comprising:
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a random access memory which stores a set of instructions that comprise a control program, which stores an input image table that contains status bits that correspond to input devices on the controlled system, and which stores an output image table that contains status bits that correspond to output devices on the controlled system, said control program including status bit instructions which identify a selected status bit to be operated upon and which includes an operation code that identifies a selected operation to be performed on the identified status bit; a processor connected directly to the random access memory and including program instruction counter means for sequentially reading out of memory said control program insructions, means responsive to status bit instructions read from said memory for reading out of memory the selected status bit identified by a status bit instruction, and means responsive to the operation code in a status bit instruction read from memory for performing the identified selected operation on the identified status bit read from said memory, said processor being operable to cyclically execute the control program and to thereby continuously update the status of the output image table in response to the status of the input image table; and a scanner circuit connected directly to said random access memory and coupled to the input and output devices on the controlled system, said scanner circuit having I/O address counter means for addressing sets of status bits in said random access memory and scanner control means connected to said processor and said random access memory for periodically interrupting operation of said processor and coupling an addressed set of status bits between said random access memory and the controlled system. - View Dependent Claims (19, 20, 21)
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Specification