Method and apparatus for automatic sales tax computation

• US 3,944,801 A
• Filed: 09/03/1974
• Issued: 03/16/1976
• Est. Priority Date: 09/03/1974
• Status: Expired due to Term

• Current Assignee: Digital Computer Controls Incorporated
• Original Assignee: Digital Computer Controls Incorporated
• Inventors: Montana, Richard L.
• Primary Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/502,853
• Time in Patent Office: 560 Days
• Field of Search: 235/61 A, 235/61 M, 235/156, 340/172.5, 444/1
• US Class Current: 705/19
• CPC Class Codes: G06Q 20/207 Tax processing
• CPC Class Codes: G06Q 40/02 Banking, e.g. interest calculation or account maintenance credit or loans G06Q40/03

Abstract

A device is provided for the exact automatic computation of sales tax rather than calculation of tax as a percentage. In the disclosure, a first subset of tax cutoff values and a second subset of repeating increments of values, corresponding to repeating increments of tax, are stored in a memory. The amount on which the tax is to be calculated is entered into a register and compared in a CPU to the total vlaue of the first subset. The CPU provides a zero output to a register when the amount is less than the first subset. When the amount is larger, the CPU subtracts the first subset from the amount. A divider in the CPU divides the remainder by the total value of the second subset. A multiplier multiplies the whole number quotient, of the division, by a tax amount. The resultant is entered into a register. A comparer and related circuitry compares the quotiant to a first and successive increments in the second subset until a successive one of the increments exceeds the remainder and stores the incremental tax values. In response to the exceeding increment, the CPU terminates the comparing operation and causes the device to indicate the stored, exact tax value.

Claims

1. An automatic sales tax computer comprising, in combination

an amount register for storing a signal indicative of a taxable amount;

a tax register for storing a signal indicative of an amount of tax;

a memory for selectively providing a signal indicative of a first sum equal to the upper limit of a first range of values, a signal indicative of a second sum equal to a second range of values greater than said first range of values, and signals respectively indicative of successive increments within said first and second ranges of values;

means for accessing the first sum from said memory for comparison to the number in said amount register and for providing a zero output to the tax register when the amount is less than said first sum and for subtracting the first sum from the amount when the amount is greater than the first sum;

means for accessing the second sum from said memory and for dividing the remainder thereby; and

multiplication means for multiplying the whole number quotient of the aforesaid division by a tax amount and entering the result in said tax register, and means for comparing the quotient in sequence to a first increment within the second range and the sum of the first increment and successive increments accessed from said memory and means coupled for incrementing the signal in the tax register for each increment accessed from said memory, and means responsive to the aforesaid comparison for terminating further accessing of increments from the memory when the sum of the first increment and successive increments exceeds the remainder, whereby a signal indicative of the exact tax on the taxable amount is provided in the tax register.

2. An automatic sales tax computer according to claim 1 wherein said memory is provided with further storage locations for providing signals indicative of successive increments in the first range and further comprising means responsive to a comparison indicating a taxable amount less than said first sum for initiating a comparison of the taxable amount to a first increment in the first range and successive comparison to the sum of the first increment and successive increments, and means for incrementing the signal in the tax register for each increment beyond a pre-selected increment, and comparison means for terminating accessing of increments from said memory when the sum of the first increment and successive increment exceeds the signal indicative of the taxable amount.

3. An automatic sales tax computer according to claim 1 wherein said memory is provided including means for providing a first signal indicative of a first range in one increment.

4. An automatic sales tax computer according to claim 3 wherein said first range is selected to correspond to a value of zero to a number corresponding to a highest value of a sales tax range on which there is no tax, and including means in said memory for providing the first signal when addressed by an address indicative of the first range.

5. An automatic sales computer according to claim 4 wherein the second range is selected to begin at the value of the first taxable amount and said memory is provided storing increments corresponding to amount for which tax increases one cent.

6. An automatic sales tax computer according to claim 5 further comprising means for displaying the number indicated by the signal in said tax register.