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Electronic security apparatus

  • US 3,944,976 A
  • Filed: 08/09/1974
  • Issued: 03/16/1976
  • Est. Priority Date: 08/09/1974
  • Status: Expired due to Term
First Claim
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1. Electronic security apparatus comprising:

  • a first set of a plural number N of logic elements capable of attaining distinct logic states interconnected to provide a plurality of logic states or bits;

    first gate means having an input connected to the output of the Nth logic element of the first set and having an output connected to the first of the N number of logic elements of the first set for operation therewith as a shift register which produces a selectably changeable pattern of logic states in the first set;

    a second set of a plural number of at least N logic elements capable of attaining distinct logic states and interconnected to provide a plurality of logic states or bits;

    second gate means having an input connected to the output of the Nth logic element of the second set and having an output connected to the first of the N number of logic elements of the second set for operation therewith as a shift register which produces a selectably changeable pattern of logic states in the second set;

    third gate means having an input port connected to the output of the Nth logic element of the first set and having another input port for receiving manifestations of logic states attained by the second set of logic elements for serial comparison with the logic states attained by said first set of logic elements to provide an output signal indicative of parity of compared logic states;

    transfer means selectively enabled to couple the logic elements of the first set to the logic elements of the second set for selectively transferring the pattern of logic states from one set to the other set of logic elements;

    means for selectively coupling an output of said second set of logic elements to said other input port of the third gate means for selectively comparing therein the logic states serially received from said first and second sets of logic elements; and

    utilization means connected to said third gate means for responding to said output signal upon occurrence of parity of compared logic states.

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