Pseudo-random code generator

• US 3,946,215 A
• Filed: 09/30/1974
• Issued: 03/23/1976
• Est. Priority Date: 09/30/1974
• Status: Expired due to Term

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: May, Jack L.
• Primary Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/510,503
• Time in Patent Office: 540 Days
• Field of Search: 235/152, 331/78
• US Class Current: 708/252
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: G06F 7/582 Pseudo-random number generators
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A pseudo-random bit generator forms a portion of the pseudo-random code generator, and provides square wave output bits over a defined frequency spectrum on a plurality of parallel output lines. The bits present on a selected number of output lines in sequence define a binary number, which is compared with an accumulated count present in a counter driven by a clock running at a predetermined frequency. A correct comparison resets the counter, shifts the pseudo-random bit generator, and shifts a past-history shift register which contains a portion of the output of the pseudo-random code generator. The output from the past-history shift register, and the square wave output bits on certain other parallel output lines from the random bit generator are applied as inputs to respective logic probability circuits. The logic probability circuits are connected to an output logic circuit, the output of which is the pseudo-random code signal, a series of square waves occurring pseudo-randomly over a frequency spectrum which is adjustable by altering the parameters of the various logic probability circuits.

Claims

1. An apparatus for generating a pseudo-random code signal, comprising:

first circuit means operative to produce a plurality of first output bits which define a pseudo-random sequence;

at least one logic gating means responsive to more than one of said first output bits, said logic gating means providing a logic output bit, said logic output bit and selected other first output bits defining a first count;

clock means generating a clock signal of predetermined frequency;

counter means responsive to said clock signal and operative to count from a reference count;

means operative to compare the count of said counter means with said first count, and to generate a comparator signal in response to an equality therebetween;

means responsive to said comparator signal for resetting said counter means to said reference count;

means coupling said comparator signal to said first circuit means, said first circuit means producing in response to said comparator signal a new pseudo-random bit sequence; and

,

means controlled by said comparator signal to produce successive second output bits defining the pseudo-random code signal.

2. An apparatus of claim 1, wherein said second output bit producing means includes storage means having a series of outputs, and means for applying a portion of said code signal to said storage means, and further includes second logic means responsive to said storage means outputs, and to selected ones of said first output bits for producing successive output bits under the control of said comparator signal.

3. An apparatus of claim 2, wherein said storage means is a linear shift register, and wherein said linear shift register is responsive to said comparator signal to enter the portion of the code signal then presented to said storage means by said applying means.

4. An apparatus of claim 1, wherein said counter means has a counting cycle at least equal to the largest possible first count.

5. An apparatus of claim 1, wherein said first output bits are square waves, and wherein the code signal is a square wave signal.

6. An apparatus of claim 1, wherein said first circuit means includes a linear shift register having an input and output, and an odd/even parity generator, wherein said linear shift register is in parallel connection with said odd/even parity generator, wherein said odd/even parity generator is responsive to selected ones of said first output bits to produce a bit series, the bits in said bit series being applied to the input of said linear shift register in response to said comparator signal.

7. An apparatus of claim 6, wherein said odd/even parity generator is operative to sum the number of selected first output bits having a first magnitude, and to produce a bit having a first magnitude when said sum is even, and a second magnitude when said sum is odd.

8. An apparatus of claim 6, including means for selectively coupling each of said first output bits to said odd/even parity generator.

9. An apparatus of claim 1, including means for delaying the resetting of said counter means until said new pseudo-random bit sequence has been produced.

10. An apparatus for generating a pseudo-random code signal, comprising:

first circuit means operative to produce a plurality of first output bits which define a pseudo-random sequence, each of said first output bits varying between two levels of magnitude according to a known first probability;

second circuit means responsive at its input to selected first output bits for generating a plurality of counter input bits, at least one of which varies between two levels of magnitude according to a probability different than said known first probability, said counter input bits defining a first count;

clock means generating a clock signal of predetermined frequency;

counter means responsive to said clock signal and operative to count from a reference count;

means operative to compare the count of said counter means with said first count, and to generate a comparator signal in response to an equality therebetween;

means responsive to said comparator signal for resetting said counter means to said reference count;

means coupling said comparator signal to said first circuit means, said first circuit means producing in response to said comparator signal a new pseudo-random bit sequence; and

,

means controlled by said comparator signal to produce successive second output bits defining the pseudo-random code signal.