System for synchronizing local pseudo-noise sequence to a received baseband signal

• US 3,947,634 A
• Filed: 11/21/1974
• Issued: 03/30/1976
• Est. Priority Date: 11/21/1974
• Status: Expired due to Term

• Current Assignee: E-Systems LLC
• Original Assignee: NCR Corporation
• Inventors: Betts, William L.
• Primary Examiner(s): Mayer, Albert J.
• Application Number:
  US05/525,910
• Time in Patent Office: 495 Days
• Field of Search: 178/67, 178/69.5 R, 178/69.5 DC, 178/69.5 G, 325/320, 325/321, 331/78
• US Class Current: 375/367
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/043 Pseudo-noise [PN] codes variable during transmission synchronisation of spread spectrum receivers H04B1/69

Abstract

The present system generates a local PN (Pseudo Noise) sequence demodulation bit stream in synchronism with the modulation sequence of a received baseband signal. The system is comprised of a PN sequence generator for generating a local PN sequence signal in response to the pulse rate of a clock signal. A digital delay line generates early and late phases of the local PN sequence, which phases are correlated with the modulation sequence of the received signal. Early correlation causes pulses to be inserted into the train of clock pulses while late correlation causes pulses to be deleted from the train of clock pulses. A phase error less than a predetermined range (dead band) results in no adjustments to the train of clock pulses.

Claims

1. A digital modulation locked loop for generating and for synchronizing a generated demodulation sequence signal with a corresponding modulation sequence in a received baseband signal, comprising in combination:

means for generating an early phase pseudo-noise demodulation sequence signal the phase of which is controlled by the pulse rate of a train of modified clock pulses, which means when in a phase locked condition maintains the phase of said pseudo-noise demodulation sequence signal advanced in phase with respect to the phase of the pseudo-noise modulation sequence of the received baseband signal;

delay means for delaying said generated early phase pseudo-noise demodulation sequence signal by fixed amounts to provide a delayed in-phase pseudo-noise demodulation sequence signal and an in-phase demodulation sequence signal;

means for correlating said early phase pseudo-noise demodulation sequence signal and the delayed in-phase pseudo-noise demodulation sequence signal with the modulation sequence signals of the received baseband signal to provide correlation signals the levels of which are indicative of the degree of correlation;

means for establishing fixed reference signals about levels encompassing the levels corresponding to desired degrees of correlation;

comparing means for comparing the levels of said correlation signals against said fixed reference signals to provide comparing signals indicative of the deviation of said correlation signals from the levels encompassed by said fixed reference signals;

clock means for providing a train of clock pulses to said means for generating an early phase pseudo-noise demodulation sequence signal; and

means for inserting or deleting pulses into said provided train of clock pulses as a function of the deviation indicated by said comparing signals so as to provide a train of modified clock pulses for increasing the correlation of said early phase pseudo-noise demodulation sequence signal and said delayed in-phase pseudo-noise demodulation sequence signal with said modulation sequence in said baseband signal to maintain synchronization between said in-phase modulation sequence signal and the corresponding modulation sequence in said received baseband signal.

2. The digital modulation locked loop according to claim 1, wherein said means for generating an early phase pseudo-noise demodulation sequence signal is comprised of:

a shift register having a plurality of stages, and having at least two inputs and an output, one of said inputs connected to receive said train of modified clock pulses, with said output connected to said delay means;

logic means connected between selected stages of said shift register and another input to said shift register for feeding back logically combined signals from said selected stages to said another input of said shift register so as to generate said early phase pseudo-noise demodulation sequence signal the phase of which is dependent on the rate of the pulses in the received train of modified clock pulses.

3. The digital modulation locked loop according to claim 1, wherein said means for correlating is comprised of:

first and second signal multipliers for multiplying said early phase pseudo-noise demodulation sequence signal and said delayed in-phase pseudo-noise demodulation sequence signal against said baseband signal, respectively;

first and second amplifier means for amplifying the product signals the levels of which are from said first and said second signal multipliers, respectively, and for providing signals indicative of the degree of correlation of the multiplied signals.

4. The digital modulation locked loop according to claim 1 and further comprising:

sampling means for sampling the deviation signals of said comparators at a preselected rate and for providing said sampled signals as inputs to said means for inserting or deleting pulses into said provided train of clock pulses.

5. A digital modulation locked loop for use with a receiver of the type that receives a baseband signal that has been phase modulated by a pseudo-noise sequence, for generating a local reference signal which reference signal is maintained substantially in-phase with the pseudo-noise modulated sequence of the received baseband signal;

clock means for providing a train of clock pulses;

gating means responsive to provided insert, or provided delete signals for inserting or deleting pulses, respectively, from said train of clock pulses to provide a train of modified clock pulses;

a pseudo-noise sequence generator responsive to the phase of said modified clock pulses for generating an early phase local pseudo-noise sequence reference signal;

a first delay means for receiving the generated signal from said pseudo-noise signal generator and for delaying said generated signal for a fixed time period so as to provide to the receiver a local pseudo-noise sequence reference signal which signal is substantially in-phase with the pseudo-noise sequence signal used to phase modulate the baseband signal received by the receiver;

second delay means for delaying the substantially in-phase local pseudo-noise sequence reference signal for a fixed time period to provide a late phase local pseudo-noise sequence reference signal;

means for correlating said early and said late phase reference signals against said received baseband signal and for providing correlation signals the levels of which are indicative of the degree of correlation;

means for establishing fixed reference signals about levels encompassing the levels corresponding to desired degrees of correlation;

comparator means for comparing the levels of said correlation signals against said fixed reference signals to provide signals indicative of the deviation of said correlation signals from the levels encompassed by said fixed reference signals; and

means for providing an insert or a delete signal to said gating means in response to the signals from said comparator means.

6. The digital modulation locked loop according to claim 5, wherein said pseudo-noise sequence generator is comprised of:

a shift register having a plurality of stages, at least two inputs and an output, one of said inputs connected to receive said provided train of modified clock pulses, and said output providing said early phase local pseudo-noise sequence reference signal;

logic means connected between selected stages of said shift register and the other input to said shift register for feeding back logically combined signals from said selected stages to said other input, so as to generate said early phase local pseudo-noise sequence reference signal at said output.

7. The digital modulation locked loop according to claim 5 wherein said means for correlating is comprised of:

first and second signal multipliers for multiplying said early and said late phase local pseudo-noise sequence reference signals respectively, against the pseudo-noise modulation sequence in said received signal; and

first and second amplifier means for amplifying the product signals from said first and said second signal multipliers, respectively, and for providing signals the levels of which are indicative of the degree of correlation of the multiplied signals.