Frequency identification circuit for broadcast traffic information reception systems

• US 3,949,401 A
• Filed: 02/21/1975
• Issued: 04/06/1976
• Est. Priority Date: 02/25/1974
• Status: Expired due to Term

• Current Assignee: Blaupunkt-Werke GmbH (Aurelius AG)
• Original Assignee: Blaupunkt-Werke GmbH (Aurelius AG)
• Inventors: Hegeler, Wilhelm, Maschmeyer, Lambert, Rasehorn, Hans
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Hearn, Robert
• Application Number:
  US05/551,689
• Time in Patent Office: 410 Days
• Field of Search: 343/200, 343/225, 325/64, 325/466, 325/48, 325/55, 325/53-54, 179/15 BP, 340/225, 340/171 R, 340/171 A, 340/171 PF, 324/77 G, 324/77 H, 328/138, 328/139
• US Class Current: 455/526
• CPC Class Codes: G08G 1/094 Hardware aspects; Signal processing or signal properties, e.g. frequency bands

Abstract

Frequencies which respectively identify a particular transmitter, and a particular program content, and which are in a very low frequency range (from between 20 to 125 kHz can be recognized, and ditigal output control signals derived representative of whether one, or both, or none of these frequencies are present by use of a frequency selection input circuit, controlled by a change-over switch to initially select recognition of the transmitter identification which, if positive, is applied through a storage circuit having a storage time substantially longer than the switch-over rate, to provide an output signal if the selected transmitter is recognized, and hold that output signal during switch-over of the program content identification signal which, if present, will be fed back through a logic circuit to hold the output of the transmitter identification circuit as identified, and if not present, permit continued switch-over of the frequency identification circuit to continue to store transmitter identification signals, if present, but permit these signals to disappear, after the storage time, if the transmitter identification signals also cease. The time delay and storage circuit preferably include operational amplifiers, and the frequency identification circuit includes a phase-locked loop.

Claims

1. Circuit arrangement for frequency identification in the field of broadcast traffic information reception in which the identification is effected in identification cycles comprising

a frequency identification circuit (1) responding to, recognizing and identifying signals (BK, DK) of different, predetermined frequencies including a region identification frequency (BK) and a traffic announcement identification frequency (DK), and providing a binary output signal indicative of the presence or absence of a selected, predetermined frequency to be identified;

a first pulse shaper (2) which has a short response time (t₁) and a long storage time (t₁) of such duration that several frequency identification cycles can be performed within the storage time period, said pulse shaper being connected to the frequency identification circuit (1) and providing, at its output (B) terminal (8) information concerning the presence of the region identification frequency (BK);

an AND-gate (4), the output (B) terminal (8) of the pulse shaper (2) being connected to one of the inputs of the AND-gate (4) and the output of the frequency identification circuit (1) being connected to a second input of the AND-gate (4);

a second pulse shaper (5) having a relatively short response delay time (t₂) and a storage time (t₂) which is short with respect to the storage time (t₁) of the first pulse shaper (2), and having its input connected to the output of the AND-gate (4);

a third pulse shaper (6) having its input connected to the output of the second pulse shaper (5), said third pulse shaper having a response delay time (t₃) which is longer than the storage time (t₂) of the second pulse shaper (5) and providing at its output (G) terminal (9) information concerning the presence of the traffic announcement identification frequency (DK),

and a frequency control circuit (7) connected to the output of said second pulse shaper (5), said frequency control circuit (7) being connected to control the recognition, or identification frequency response of said frequency identification circuit (1) to respond to, identify, and provide an output upon presence of the region identification frequency (BK) if the frequency control circuit (7) does not receive an output from the second pulse shaper (5) and to control said frequency identification circuit (7) to change its response range to identify the traffic announcement identification frequency (DK) when energized from said second pulse shaper (5);

whereby

1. absence of the region identification frequency (BK) will result in no output from the identification circuit (1) and hence continuous control by the frequency control circuit (7) to continue the state of the frequency identification circuit to select and identify said regional frequency (BK), and

2. if the region identification frequency (BK) is identified, energization of the second pulse shaper (5) will cause change in the state of the frequency control circuit (7) and hence command the frequency identification circuit (1) to change to select for identification the traffic announcement frequency (DK), energization of the output terminal (8) of the first pulse shaper (2) continuing due to the long storage time (t₁) thereof and, upon non-detection of a traffic announcement frequency (DK), reversion of the state of the frequency control circuit (7) to control the frequency identification circuit (1) to again select the region identification frequency (BK), and thus extend the storage time (t₁) of the first pulse shaper; and

,

3. if the traffic announcement identification frequency (DK) is detected, the system will be held in the state in which the frequency control circuit (7) continues to command the frequency identification circuit (1) to select and identify the traffic announcement identification frequency (DK) and simultaneously continue to energize said first pulse shaper (2), thus continuously extending the storage time (t₁) thereof.

2. System according to claim 1, wherein the frequency identification circuit (1) and the frequency control circuit (7) comprise a filter and a phase-locked loop, the phase-locked loop including a voltage-controlled oscillator, and the filter being a switchable filter, the frequency control circuit (7) controlling the voltage of the voltage-controlled oscillator, and switching of said filter (10).

3. System according to claim 1, further comprising an OR-gate, connected to supply the second input to the AND-gate, said OR-gate having as inputs:

(a) the output of the frequency identification circuit (1), and (b) the output of the third pulse shaper (6).

4. Frequency identification and control system to detect occurrence of selected frequencies in a frequency spectrum and to provide digital output signals indicative of the presence or absence of selected frequencies in a frequency spectrum comprising

a frequency identification circuit (1) having first means (10-15) selectively responding to said selected frequencies and second means (16, 17) providing a digital output signal indicative of the presence or absence of the frequency selected by said first means;

first storage means (2) having a first storage time (t₁) responsive to said frequency identification circuit (1) and providing an output signal during said storage time when the frequency identification circuit provides a digital output signal indicative of the presence of the frequency selected by said first means;

second storage means (5) having a second storage time (t₂) which is short with respect to said first storage time;

a frequency selection control circuit (7) connected to and controlling said frequency identification circuit (1) to change its frequency response from a first selected frequency to another selected frequency in dependence on the output signal from said frequency selection control circuit (7);

logic circuit means (3, 4,

     6) connected to the output of said frequency identification circuit (1) and said first storage means (2), and controlling said second storage means (5) to provide an output after said second storage time (t₂) to said frequency selection control circuit (7) to control the frequency identification circuit (1) to select a different frequency identification and to maintain the circuit for the identification of said different selected frequency for the duration of said second storage time (t₂);

the logic circuit means being further connected to the output of said second storage means (5) and providing a feedback and self-locking circuit to hold said output of said frequency identification circuit (1) in a state which will effect response of both the first storage means (2) and the second storage means (5), but permit cut-off of response of the second storage means (5) and hence reversion of the frequency control circuit (7) to command the frequency identification circuit to revert to response to the first selected frequency upon failure of the frequency identification circuit (1) to detect said other selected frequency, after lapse of said second storage time (t₂) but during continued persistence of the first storage time (t₁).

5. System according to claim 4, wherein the storage time (t₂) of said second storage means (5) is long with respect to the storage time (t₁) of said first storage means.

6. System according to claim 4, wherein said logic circuit means comprises a third storage means (6) and an AND-gate (4), the AND-gate being connected to the input of the second storage means and being effective upon conjunction of:

output from said first storage means (2) and detection of the specific frequency.

7. System according to claim 4, wherein said frequency identification circuit (1) is cyclically controlled by said frequency selection control circuit (7) to select for identification, alternately, said selected frequencies;

the storage time (t₁) of said first storage means (2) being longer than one complete cycle of change-over of frequency identification between said selected frequencies of the frequency identification circuit (1);

and wherein the logic circuit means provides an output to said second storage means (5) to in turn control the frequency selection control circuit to interrupt cyclical change-over of the frequency identification circuit (1) between said selected frequencies and instead hold said frequency identification circuit in the state which permits response to and continuous identification of said predetermined one of the selected frequencies.