Electronic security control system
First Claim
1. In a security control system having an electrically operated lock means and code input means for selectively and sequentially energizing a plurality of input lines in accordance with a predetermined combination code, the combination therewith comprising:
- valid sequence counter means having a plurality of output states and an input connected and responsive to the plurality of input lines for causing said counter means to successively assume each of its counting states in response thereto;
error detection means connected between said input lines and the output states of said valid sequence counter means for detecting the erroneous energization of one of said input lines not in conformance with the predetermined code and for disabling the control system in response thereto;
error processing circuit means coupled to the output of said error detection means including means for accumulating a preselected number of error indicating signals from said error detection means, said error processing circuit means being coupled to said valid sequence counter means for disabling said valid sequence counter means in response to said accumulation of said preselected number of error indicating signals; and
output means for selectively connecting one of the output states of said valid sequence counter means to and for operating said electrically operated lock means, whereby said valid sequence counter means must be successfully advanced to the above-mentioned selected output state without prior disablement of the control system in order to successfully operate the electrically operated lock means.
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Accused Products
Abstract
Actuation of an electrically operated lock is controlled by an electronic permutation circuit including an array of code entry push-button switches disposed for operation at the entrance to a secured area and a plurality of code selector switches mounted inside the secured area for setting a predetermined code sequence. If the correct code sequence is entered, corresponding to the setting of the code selector switches, an electronic counter is sequentially advanced to a selected terminal state determined by a code length selector switch which is connected to and for operating the electrically controlled lock. The time interval during which the lock is electrically actuated may be selected by a latch time selector switch mounted along with the code selector switches inside the secured area. The occurence of a preselected number of errors during code entry, a number which may be set by a selector switch mounted along with the other selector switches, provides for activating a penalty period during which the entire system is disabled and inoperable. The duration of the penalty time may also be varied by another selector switch. A common counting circuit is employed for the error count, penalty time and latch time modes of the system. For driving a solenoid-type lock or latch, output circuitry is provided in one embodiment to include a transistorized latch driver circuit for developing a surge current for instantaneous, positive opening of the solenoid lock or latch. In another embodiment, a digital clock and display having a 24 hour timing format is provided in combination with an elapsed day counter circuit to permit use of the system as a time lock. Opening of the lock is inhibited until the expiration of a preselected time interval which may be set to a desired number of elapsed days, hours and minutes.
56 Citations
22 Claims
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1. In a security control system having an electrically operated lock means and code input means for selectively and sequentially energizing a plurality of input lines in accordance with a predetermined combination code, the combination therewith comprising:
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valid sequence counter means having a plurality of output states and an input connected and responsive to the plurality of input lines for causing said counter means to successively assume each of its counting states in response thereto; error detection means connected between said input lines and the output states of said valid sequence counter means for detecting the erroneous energization of one of said input lines not in conformance with the predetermined code and for disabling the control system in response thereto; error processing circuit means coupled to the output of said error detection means including means for accumulating a preselected number of error indicating signals from said error detection means, said error processing circuit means being coupled to said valid sequence counter means for disabling said valid sequence counter means in response to said accumulation of said preselected number of error indicating signals; and output means for selectively connecting one of the output states of said valid sequence counter means to and for operating said electrically operated lock means, whereby said valid sequence counter means must be successfully advanced to the above-mentioned selected output state without prior disablement of the control system in order to successfully operate the electrically operated lock means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. In a security control system having an electrically operated lock and code input means mounted for access outside a secured area and a control circuit mounted for access only inside the secured area, the combination comprising:
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said code input means including a plurality of input lines connected to said control circuit in which the individual lines may be selectively energized in accordance with a predetermined code; said control circuit including a valid sequence counter means having a clocking input connected jointly to a plurality of said input lines and having a preselected number of output states and associated output lines; said control circuit further including a plurality of error detection gate means each having an input connected to said input line and another input adapted to be connected to a preselected one of said counter means output lines to cause said gate means to issue an error indicating signal in response to energization of an input thereof by the associated input line unless disabled by the appropriate output state of said counter means having the associated output line thereof connected to the other input of said gate means; said control circuit further including error processing and timing circuit means connected to said gate means and responsive to a preselected number of error indicating signals to disable said valid sequence counter means; and output circuit means for operating said lock means, said output circuit means being connected to a preselected one of said output states of said counter means designated as a terminal state so as to activate said output circuit means only upon said counter means being clocked to said preselected terminal state, whereby said electrically operated lock means is opened only after successfully clocking said counter means by said code input means through said plurality of states to reach said preselected terminal state without causing said error counting circuit means to disable said sequence counter means. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. In a security control system having an electrically operated lock means and code input means for selectively and sequentially energizing a plurality of input lines in accordance with a predetermined combination code, the combination therewith comprising:
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valid sequence counter means having a plurality of output states and an input connected and responsive to the plurality of input lines for causing said counter means to successively assume each of its counting states in response thereto; error detection means connected between said input lines and the output states of said valid sequence counter means for detecting the erroneous energization of one of said input lines not in conformance with the predetermined code and for disabling the control system in response thereto; error processing circuit means connected to said error detection means for receiving error indicating signals therefrom; said error processing circuit means having a multi-function counter means with a plurality of output states, an error number selection switch means, a penalty time selection switch means, a penalty time activate circuit means and a clock generator circuit means; said multi-function counter means having a clocking input connected to and for being clocked by said error detection means in response to said error indicating signals and by clock signals from said clock signal generator means and said multi-function counter means further having a plurality of counting modes including an error counting mode and a penalty time counting mode; said multi-function counter means in its error counting mode being connected to and cooperating with said error number selection switch means to register the number of error indicating signals set by said error number selection switch means and to cause disabling of said valid sequence counter means in response thereto; said penalty time activate circuit means being connected to said multi-function counter means and to said error number selection switch means and to said clock signal generator means to activate said clock signal generator means in response to said multi-function counter means registering the set number of error indicating signals; said multi-function counter means in its penalty time counting mode being connected to and cooperating with said penalty time selection switch means to register a predetermined number of clock signals issued by said clock signal generator means, said number of clock signals corresponding to a desired penalty time period; penalty time terminating circuit means connected to said multi-function counter means and to said penalty time switch means for enabling said valid sequence counter means in response to said multi-function counter means registering said preselected number of clock signals, whereby said valid sequence counter means is enabled upon expiration of the penalty time and said control system is restored to a condition for accepting another code entry attempt; and output means for selectively connecting one of the output states of said valid sequence counter means to and for operating said electrically operated lock means, whereby said valid sequence counter means must be successfully advanced to the above-mentioned selected output state without prior disablement of the control system in order to successfully operate the electrically operated lock means.
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21. In a security control system in which an electric solenoid serves as a selectively operated electrical lock, a solenoid driver circuit for energizing said solenoid comprising:
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switched serial discharge circuit path means adapted to be serially connected to said solenoid and including a transistor switching means for switching said circuit path means between a relatively high impedance normal state and a relatively low impedance discharge state, said transistor switching means comprising, a pair of transistors connected as a Darlington pair, and further including a transistor circuit connected to and for driving said Darlington pair of transistors in response to an electrical actuating signal, said transistor circuit having a first electrical drive stage in which said Darlington pair of transistors is driven to said relatively low impedance discharge state by capacitive saturation of the base of a first of said Darlington pair of transistors and a second stage of electrical drive in which a regulated voltage is applied to said base of said first transistor of said Darlington pair to sustain said pair of transistors in said relatively low impedance discharge state following the initial saturation drive; and a capacitive charge storage means for accumulating an electrical charge and for being connected accross said discharge circuit path means for dumping said electrical charge through said solenoid in response to said transistor switching means being switched to its low impedance discharge state. - View Dependent Claims (22)
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Specification