Implicit ratio computer for sequential signals

• US 3,955,096 A
• Filed: 06/19/1975
• Issued: 05/04/1976
• Est. Priority Date: 06/19/1975
• Status: Expired due to Term

• Current Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Inventors: Faulhaber, Mark Edwin
• Primary Examiner(s): Smith, Alfred E.
• Assistant Examiner(s): LaRoche, E. R.
• Application Number:
  US05/588,643
• Time in Patent Office: 320 Days
• Field of Search: 250/565, 250/573, 250/575, 250/214 R, 250/236, 356/97, 356/93, 356/201, 356/205, 324/140 D, 328/161
• US Class Current: 250/565
• CPC Class Codes: G01J 1/16 using electric radiation detectors G01J1/20 takes precedence
• CPC Class Codes: G06G 7/161 with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form pulse modulators H03K7/00

Abstract

An electrical signal ratioing circuit for a source delivering an electric analog pulse signal sequence having compensating means for removing the effects of background influences, such as amplifier signal offsets and extraneous illumination, and integrating means eliminating the effect of line voltage variations and changes in optical and electrical system gains on the ratios so produced.

Claims

1. In an electrical signal ratioing circuit for a source delivering an electric analog signal pulse sequence comprising measured parameter signals A₁, A₂ . . . A_n, and at least one reference signal R,

signal gating and timing means having signal identification means maintaining time coordination with said signal pulse sequence, and gate actuating means responsive to said signal identification means actuating, for predetermined time durations, the respective gates corresponding to said signals A₁, A₂ . . . A_n, and, R

an amplifier which imparts a gain G to said signals,

a gated integrator which, during the gated period wherein said reference signal R is delivered, has a first input terminal receiving the sum of said signal pulse sequence of a given polarity from said amplifier and a substantially constant d-c reference voltage K of opposite polarity, and a second input terminal connected to ground,

means supplying said integrator output to control a gain -- determining resistance for said amplifier, and

individual parallel sampling circuits gating the individual signal ratios KA₁ /R, KA₂ /R . . . KA_n /R during the successive time periods wherein each is output from said amplifier.

2. In an electrical signal ratioing circuit for a source delivering an electrical analog signal pulse sequence having, additionally, a background signal B the apparatus of claim 1 wherein there is interposed between said amplifier and said gated integrator a gated clamp which subtracts the product (GB) of said amplifier gain G and said background signal B from said signal pulse sequence, and said individual signal ratios KA₁ /R, KA₂ /R . . . KA_n R are output from said gated clamp.

3. The apparatus of claim 2 wherein said parameter signals A₁, A₂ . . . A_n and said reference signal R are the respective electric analog signals of a filter photometer.

4. Apparatus according to claim 2 wherein said gated clamp comprises an operational amplifier having positive and negative polarity input terminals and first and second series - connected resistor pairs, each resistor having substantially the same resistance value, both resistor pairs being connected at one end to the output side of said voltage amplifier and said first resistor pair being connected to ground at its other end whereas said second resistor pair is connected at its other end to the output side of said operational amplifier, a feedback supply lead connected between the two resistors of said second resistor pair and the negative polarity input terminal of said operational amplifier, a signal input lead connected between the two resistors of said first resistor pair and said positive polarity input terminal of said operational amplifier, a voltage level-maintaining capacitor connected between said positive polarity input terminal of said operational amplifier and ground, and switching means responsive to said gating and timing means interposed between the midpoint of said first resistor pair and the ungrounded side of said capacitor.

5. Apparatus according to claim 2 wherein said amplifier is an operational amplifier having positive and negative polarity input terminals, said positive polarity input terminal being coupled through a capacitor to receive said electric analog signal pulse sequence, a voltage level-maintaining resistor connected between the positive terminal of said voltage amplifier and said coupling capacitor to ground, a feedback resistor connected between the output side of said voltage amplifier and said negative polarity input terminal, and an enclosed light feedback element comprising a light-sensitive resistor having a resistance varying inversely with the intensity of light impinging thereon connected between said negative terminal of said voltage amplifier and ground, and a light-emitter constituting the light source for said light-sensitive resistor connected as feedback between said integrator output and ground.

6. The apparatus of claim 2 wherein said individual parallel sampling circuits gating said individual signal ratios KA₁ /R, KA₂ /R . . . KA_n /R are each provided with a logarithmic read-out circuit having, in the order recited, a zero adjustment potentiometer delivering a voltage proportional to the product ZA/R, and means summing said product ZA/R with a constant voltage of opposite polarity to give a voltage closely approximating -log A/R for read-out via a span adjustment sub-circuit.