Switching circuit having floating gate mis load transistors

• US 3,955,098 A
• Filed: 08/08/1974
• Issued: 05/04/1976
• Est. Priority Date: 10/12/1973
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kawamoto, Hiroshi
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): Anagnos, L. N.
• Application Number:
  US05/495,769
• Time in Patent Office: 635 Days
• Field of Search: 307/205, 307/213, 307/214, 307/251, 307/304, 307/DIG. 4
• US Class Current: 326/112
• CPC Class Codes: H03K 17/60 the devices being bipolar transistors bipolar transistors having four or more electrodes H03K17/72
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12
• CPC Class Codes: H03K 19/09441 of the same canal type
• CPC Class Codes: H03K 5/023 using field effect transistors

Abstract

A switching circuit comprises a driving MIS field-effect transistor, and a load MIS field-effect transistor, the gate of which is electrically floating and is so charged as to produce a gate voltage greater than the supply voltage of the load MIS field-effect transistor.

Claims

1. In a switching circuit including a first driving metal-insulator-semiconductor transistor and a first load metal-insulator-semiconductor transistor connected in series with a source of supply voltage, and a second driving metal-insulator-semiconductor transistor and a second load metal-insulator-semiconductor transistor connected in series with said source of supply voltage,

the improvement wherein the gate electrodes of said first and second load transistors are connected in common, electrically float and have a prescribed quantity of charge stored thereon, so that the gate voltages of said load transistors exceed said power supply voltage.

2. In a switching circuit including a driving metal-insulator-semiconductor transistor and a load metal-insulator-semiconductor transistor connected in series with a source of supply voltage, the improvement wherein the gate electrode of said load transistor electrically floats and has a prescribed quantity of charge stored thereon so that the gate voltage of said load transistor exceeds said power supply voltage, and

further comprising means for applying said prescribed quantity of charge to the gate electrode of said load transistor, said means comprising a writing-in metal-insulator-semiconductor transistor having its gate electrode connected to the gate of said load transistor and its source and drain electrodes connected to respective voltage sources, the difference between which is greater than said source of supply voltage, for effecting avalanche breakdown in the insulating layer of said writing-in transistor, to charge the gate thereof to a potential greater than said source of supplying voltage, and thereby charge the gate electrode of said load transistor.

3. A circuit comprising:

a first plurality of insulated gate field effect transistors;

a second plurality of insulated gate field effect transistors;

first and second terminals to which first and second sources of reference potential are supplied;

each transistor of said first plurality of transistors being connected in series with a respective transistor of said second plurality of transistors, between said first and second terminals;

input terminals connected to the gate electrodes of said first plurality of transistors;

output terminals connected to the common connections of said first and second pluralities of transistors, respectively; and

wherein

the gate electrodes of said second plurality of transistors are connected in common, are electrically floating and have a prescribed amount of charge stored therein, so that the effective gate voltage of said second plurality of transistors exceeds the difference between said first and second sources of reference potential.

4. A circuit according to claim 3, wherein said first source of reference potential is ground potential.

5. A circuit comprising:

a first insulated gate field effect transistor;

a second insulated gate field effect transistor;

first and second terminals to which first and second sources of reference potential are supplied;

said first and second transistors being connected in series between said first and second terminals;

an input terminal connected to the gate electrode of said first transistor;

an output terminal connected to the common connection of said first and second transistors; and

wherein

the gate electrode of said second transistor is electrically floating and has a prescribed amount of charge stored therein, so that the effective gate voltage of said second transistor exceeds the difference between said first and second sources of reference potential;

and further including

a third insulated gate field effect transistor having its gate electrode effectively electrically floating and connected to the gate electrode of said second transistor, and having its source and drain electrodes connected to respective sources of supply voltage, the difference between which exceeds the difference between said first and second sources of reference potential, thereby effecting avalanche breakdown in the insulating layer of said third transistor, to charge the gate electrode thereof to a potential greater than the difference between said second and first sources of supply voltage and thereby charge the gate electrode of said second transistor.

6. A circuit according to claim 5, wherein said first source of reference potential is ground potential.