×

Pipeline walsh-hadamard transformations

  • US 3,956,619 A
  • Filed: 03/31/1975
  • Issued: 05/11/1976
  • Est. Priority Date: 03/31/1975
  • Status: Expired due to Term
First Claim
Patent Images

1. A machine for receiving an input sequence signal of serial, data samples, there being 2P signals in each sequence, and for producing therefrom a serial output signal representative of the sequency ordered coefficients of a binary, orthogonal transform of said input data signals, comprising in combination:

  • a. an ordered set of p signal processing modules, each of said processing modules having an associated order number i (i = 1, p), each of said modules further having a signal input port, a signal output port, and control input ports;

    said modules being connected in an ordered cascade, wherein said input sequence signal is applied to said signal input port of the first ordered of said modules and said output signal is received from said signal output port of the pth ordered of said modules, each of said signal processor modules further comprising;

    an ordered set of 2i signal storage elements, where i represents the order number of said signal processor module, said storage elements being organized as a first ordered subset comprising the 2i-1 lowest ordered storage elements of said set and a second ordered subset comprising the 2i-1 highest ordered storage elements in said set;

    switching means connected for sequentially applying signals from said input port to each of said storage elements in said ordered set in order and in response to signals from said control ports;

    arithmetic circuit means, connected for sequentially receiving pairs of signals from pairs of said storage elements, said pairs of said storage elements including correspondingly ordered storage elements taken from said first subset and from said second subset, and for producing therefrom, at the output port of said signal processor module and in response to signals from said control port, a sum signal representative of the sum of said pair of signals and a difference signal representative of the difference of said pair of signals;

    b. control means connected for providing a plurality of control signals to the control signal ports of each of said signal processor modules, said control signals being connected to induce said arithmetic means to sequentially produce said sum signals and said difference signals from each of said received pairs of signals whereby said signals transform coefficients of said input sequence of data signals are extracted.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×