Pipeline walsh-hadamard transformations

• US 3,956,619 A
• Filed: 03/31/1975
• Issued: 05/11/1976
• Est. Priority Date: 03/31/1975
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Mundy, Joseph L., Joynson, Reuben E.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/563,820
• Time in Patent Office: 407 Days
• Field of Search: 235/193, 235/152, 235/156, 235/197, 179/15 BC, 328/167
• US Class Current: 708/410
• CPC Class Codes: G06F 17/145 Square transforms, e.g. Hadamard, Walsh, Haar, Hough, Slant transforms

Abstract

A machine for generating sequency ordered Walsh transform coefficients from an input data sequence comprises an ordered cascade of identically configured signal processor modules. Each module receives two sequency ordered transform blocks of Walsh transform co-efficients and by alternately adding and subtracting corresponding elements in those blocks produces the transform co-efficients of next higher order.

Claims

1. A machine for receiving an input sequence signal of serial, data samples, there being 2^P signals in each sequence, and for producing therefrom a serial output signal representative of the sequency ordered coefficients of a binary, orthogonal transform of said input data signals, comprising in combination:

a. an ordered set of p signal processing modules, each of said processing modules having an associated order number i (i = 1, p), each of said modules further having a signal input port, a signal output port, and control input ports;

said modules being connected in an ordered cascade, wherein said input sequence signal is applied to said signal input port of the first ordered of said modules and said output signal is received from said signal output port of the p^th ordered of said modules, each of said signal processor modules further comprising;

an ordered set of 2ⁱ signal storage elements, where i represents the order number of said signal processor module, said storage elements being organized as a first ordered subset comprising the 2^i-1 lowest ordered storage elements of said set and a second ordered subset comprising the 2^i-1 highest ordered storage elements in said set;

switching means connected for sequentially applying signals from said input port to each of said storage elements in said ordered set in order and in response to signals from said control ports;

arithmetic circuit means, connected for sequentially receiving pairs of signals from pairs of said storage elements, said pairs of said storage elements including correspondingly ordered storage elements taken from said first subset and from said second subset, and for producing therefrom, at the output port of said signal processor module and in response to signals from said control port, a sum signal representative of the sum of said pair of signals and a difference signal representative of the difference of said pair of signals;

b. control means connected for providing a plurality of control signals to the control signal ports of each of said signal processor modules, said control signals being connected to induce said arithmetic means to sequentially produce said sum signals and said difference signals from each of said received pairs of signals whereby said signals transform coefficients of said input sequence of data signals are extracted.

2. The machine of claim 1 wherein said control means are further connected to induce said arithmetic circuit means in said first ordered module to sequentially produce said sum and said difference signal from each of said received signal pairs.

3. The machine of claim 2 wherein said control means are further connected to induce each of said arithmetic circuit means in each of said modules having an order number , i being equal to or greater than 2, to sequentially produce said sum signals and said difference signals from a first received signal pair and said difference signals and said sum signals from a next received signal pair.

4. The machine of claim 3 wherein said control means are further connected to induce said signal processor modules to operate synchronously in response to a periodic clock signal.

5. The machine of claim 4 wherein said control means are further connected to induce each of said arithmetic circuit means in each of said signal processor modules having even order numbers, to produce a sum signal at such times as each of said arithmetic circuit means in each of said signal processor modules having odd order numbers, i being greater than 1, produce a difference signal.

6. The machine of claim 5 wherein said plurality of control signals comprise a first square wave having a period equal to twice the period of said periodic clock signal, said first square wave being applied to a control port of said first signal processor module.

7. The machine of claim 6 wherein said plurality of control signals comprise a second square wave having a period equal to four times the period of said periodic clock signal, said second square wave being applied to the control ports of said processor modules of even order number, .

8. The machine of claim 7 wherein a complement wave of said second square wave is applied to the control ports of said signal processor modules having odd order numbers, i, i being greater than 1.

9. The machine of claim 8 wherein said input sequence signal comprises eight samples;

said ordered set of signal processor modules comprises three signal processor modules, the first of said processor modules comprises two of said storage elements, the second of said processor modules comprises four of said storage elements, and the third of said processor modules comprises eight of said storage elements; and

wherein said arithmetic circuit means in said third module produce said sum signals at such times as said arithmetic circuit means in said second module produce said difference signals.

10. The machine of claim 1 wherein said storage elements are analog sample-and-hold circuits.

11. The machine of claim 10 wherein said arithmetic circuit means are operational amplifiers.

12. The machine of claim 1 wherein said storage elements are digital storage means.

13. The machine of claim 12 wherein said arithmetic circuit means are digital logic circuits.

14. The machine of claim 1 wherein each of said arithmetic circuit means further comprise two temporary storage elements connected for receiving and temporarily storing the values of one of said signal pairs.

15. A machine for sequentially receiving 2t sample blocks of an input signal representative of the values of the order t, sequency ordered Walsh transform coefficients of successive t sample blocks of a data set and for extracting therefrom serial output characters representative of the values of the successive, order 2t, sequency ordered Walsh transform coefficients of sequential, 2t sample blocks of said data set;

wherein t = 2ⁿ, n being an interger;

comprising in combination;

a first storage register comprising t ordered data storage elements;

a second storage register comprising t ordered data storage elements;

input switching means, connected for receiving said input signal and for transferring the values of a first block of said input samples, in order, into the ordered elements of said first storage register and for transferring the values of a next block of said input samples, in order, into the ordered elements of said second storage register; and

arithmetic circuit means connected for sequentially receiving values from said ordered elements from said first storage register and for pairing said values with values received from storage elements of corresponding order in said second storage register and for sequentially producing signals representative of the sums and of the differences of said value pairs whereby said sequency ordered transform coefficients are extracted.

16. The machine of claim 15 wherein said arithmetic means is further connected for successively producing said sum signal and said difference signal from said pair of values received from a first ordered pair of said storage elements and for successively producing said difference signal and said sum signal from a pair of said values received from a next ordered pair of said storage elements.

17. The machine of claim 15 wherein said storage elements comprise binary data storage means and wherein said arithmetic means comprise digital logic circuits.

18. The machine of claim 17 wherein each of said samples consists of one data bit.

19. The machine of claim 15 wherein said storage elements comprise analog sample-and-hold circuits and said arithmetic means comprise operational amplifiers.

20. The machine of claim 15 wherein t equals 2.

21. The machine of claim 15 wherein t equals 4.