Method for constructing a rom for redundancy and other applications

• US 3,959,047 A
• Filed: 09/30/1974
• Issued: 05/25/1976
• Est. Priority Date: 09/30/1974
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Alberts, Gene Stoddard, Farrar, Paul Alden, Hallen, Robert Lee
• Primary Examiner(s): Powell, William A.
• Application Number:
  US05/510,667
• Time in Patent Office: 603 Days
• Field of Search: 156/8, 156/11, 156/17, 156/18, 29/576, 29/577, 29/589, 427/88, 427/89, 427/91
• US Class Current: 438/601
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is an improved method for manufacturing semiconductor integrated circuitry whereby interconnection pad limiting metallurgy and read only fusible link memory structure is simultaneously formed by first blank depositing a composite metal film followed by in situ forming pad metallurgy and said read only link structure utilizing photoresist and etch techniques. Said read only memory link structure is utilized for directing the use of redundant lines in place of defective array bits.

Claims

1. In a method for manufacture of integrated semiconductor structure the improvement comprising blanket depositing a composite metal film upon a passivating film of said structure followed by simultaneously forming interconnecting pad limiting via metallization and a redundancy read only metal link pattern thereon.

2. A method in accordance with claim 1 wherein said composite metal film is a successive depositing of chromium, copper and gold.

3. A method in accordance with claim 1 wherein said semiconductor structure is formed of silicon.

4. A method in accordance with claim 1 wherein said passivating film is silicon dioxide.

5. A method in accordance with claim 1 wherein said passivating film is polyimide.

6. A method in accordance with claim 1 wherein said passivating film is a composite layer of quartz and polyimide.

7. A method in accordance with claim 2 wherein said composite metal film is vacuum deposited.

8. A method in accordance with claim 1 wherein said link structure has a width of 3/10,000 inch to 7/10,000 inch and a length of about 5/1,000 inch.

9. A method in accordance with claim 1 wherein said composite metal link structure comprises 750 angstroms thickness chromium, 500 angstroms of Cr-Cu-Au, 16,500 angstroms copper, 2,200 angstroms gold and is deposited on a passivating film which is a composite of polyimide over quartz with said deposition at approximately 250°

C.

10. A method in accordance with claim 1 wherein said composite metal link structure comprises 800 angstroms thickness chromium, 9,000 angstroms copper and 1,400 angstroms gold.