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Frequency synthesizer having fractional frequency divider in phase-locked loop

  • US 3,959,737 A
  • Filed: 11/18/1974
  • Issued: 05/25/1976
  • Est. Priority Date: 11/18/1974
  • Status: Expired due to Term
First Claim
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1. A frequency synthesizer, which comprises:

  • a voltage-tuned oscillator, the output frequency of which is monotonically related to a d.c. potential applied to the tuning port thereof;

    a digital divider connected to the output of said voltage-tuned oscillator, said digital divider dividing the output frequency of said voltage-tuned oscillator by a factor of N, where N is any integer or fractional number greater than unity;

    means connected to said digital divider, for altering the value of said factor N;

    a source of a reference frequency signal;

    means connected to the output of said digital divider and to said source of a reference signal, for comparing the phase of said reference frequency signal with the phase of the divided output of said voltage-tuned oscillator, thereby to generate an error signal if there is any difference in phase; and

    means for supplying said error signal to the tuning port of said voltage-tuned oscillator whereby said oscillator alters its output frequency, and hence the output frequency of the synthesizer, in an offsetting manner to reduce said error signal towards zero;

    wherein said digital divider produces an unwanted ramp signal which tends to produce spurious sidebands in the output of said voltage-tuned oscillator, and said synthesizer further comprises a sideband reduction circuit having an input connected to the output of said digital divider and an output connected to said supplying means, said sideband reduction circuit generating a ramp signal of similar frequency, amplitude and shape to said unwanted ramp signal, but of opposite phase, whereby said unwanted ramp signal is canceled in said supplying means.

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