Multiprocessing system implemented with microprocessors

• US 3,959,775 A
• Filed: 08/05/1974
• Issued: 05/25/1976
• Est. Priority Date: 08/05/1974
• Status: Expired due to Term

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: GTE Automatic Electric Laboratories Incorporated
• Inventors: Holden, James R., Valassis, John G.
• Primary Examiner(s): Nusbaum, Mark E.
• Application Number:
  US05/494,446
• Time in Patent Office: 659 Days
• Field of Search: 340/172.5, 445/1
• US Class Current: 710/113
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A bus assigner in an electronic data processing system for selectively assigning access to a system bus to one of a plurality of microprocessors comprising a multiprocessing system. In an embodiment of the present invention, logic circuitry is provided for assigning a priority of operation to each of the microprocessors, each microprocessor having a different assigned priority. The bus assigner selectively assigns access to the sysstem bus to the microprocessor having the highest priority whenever one or more of the microprocessors requests access to the system bus. In an alternative embodiment, the bus assigner sequentially scans the microprocessors for requests for access to the system bus and assigns access to the system bus in the order in which the requests are received by the bus assigner as it scans the microprocessors.

Claims

1. An expandable modular control system for controlling a second controlled system being monitored by said expandable modular control system comprising:

means comprising a sense point module and a control point module, each of said modules comprising an array of memory devices corresponding to a plurality of n-bit words, each n-bit word having a corresponding memory address associated therewith,

said sense point module being coupled to and monitoring said second system, said second system generating n-bit data words which are stored in said sense point module memory devices at assigned ones of said memory addresses responsive thereto,

said control point module being coupled to and controlling said second system in accordance with n-bit control words stored in said control point module memory devices at assigned ones of said memory addresses;

external modular memory means for storing said n-bit words at assigned memory addresses therein;

multiprocessing means including a plurality of microprocessor modules for asynchronously processing said n-bit data words to generate said n-bit control words for controlling said second system;

system bus means including extended memory address bus means and extended data transfer bus means intercoupling said multiprocessing means with said external modular memory means and said sense point and control point modules,

said modular microprocessors selectively addressing said memory addresses in said modular external memory means and said sense point and control point modules via said extended memory address bus means to transfer said n-bit words therebetween via said extended data transfer bus means for processing by said multiprocessing means to control said second system; and

bus assigner means including logic means assigning a priority of operation to each of said microprocessor modules for selectively assigning access to said system bus means to said microprocessor modules, each of said microprocessor modules having a different assigned priority, said bus assigner means assigning use of said system bus means to said microprocessor module having the highest priority whenever one or more of said microprocessor modules requests access to said external memory, said bus assigner means permitting transfer of said n-bit words between the selected one of said microprocessor modules having priority and the external modular memory means, the sense point module and the control point module.

2. Apparatus in accordance with claim 1 including input/output means comprising one or more input/output interface modules having corresponding input/output devices associated therewith for inputing n-bit words to said multiprocessing means via said system bus means under the control of said bus assigner means and for outputing processed n-bit words therefrom.

3. Apparatus in accordance with claim 2 wherein said system bus means includes extended input/output address bus means and extended input/output data transfer bus means intercoupling said input/output interface modules and said multiprocessing means for respectively addressing a particular one of said input/output interface modules and transferring n-bit data between said addressed input/output interface module and said multiprocessing means.

4. Apparatus in accordance with claim 1 wherein each of said microprocessor modules comprises a microprocessor device mounted on a printed circuit card.