Signal correlator

• US 3,961,203 A
• Filed: 01/09/1975
• Issued: 06/01/1976
• Est. Priority Date: 01/09/1975
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Hutch, Frederick
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US05/539,857
• Time in Patent Office: 509 Days
• Field of Search: 307/232, 307/236, 307/230, 328/57, 328/109, 328/118, 328/119, 328/120, 340/146.1 AB, 340/146.1 F, 340/146.1 BA
• US Class Current: 327/28
• CPC Class Codes: G06F 11/1497 Details of time redundant execution on a single processing unit
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

A signal correlator for correlating pulse pairs received over a data transmission line as alternating positive and negative pulses representing data "1'"'"'s" and "O'"'"'s." The reception of a logic "1" is affirmed by testing for a negative polarity pule pulse an initial positive polarity pulse received over the transmission line. Conversely, the reception of a logic "O" is affirmed by testing for a positive pulse following an initial negative pulse received over the transmission line. The first pulse of a pulse pair received over the transmission line is temporarily stored in a flip-flop and the stored pulse value is compared by a comparator with the second pulse when it arrives. An error signal is developed by the comparator in the event that an error is detected between the stored pulse value and the second pulse with which it is compared in either pulse pair combination.

Claims

1. A correlator comprising:

an input signal receiving means for receiving pulse pair data signals,

flip-flop means for storing a first pulse of said pulse pairs, and

means for comparing a second pulse of said pulse pairs with said stored first pulse of said pulse pairs to detect the presence of an error in the received pulse pairs.

2. A correlator as set forth in claim 1 wherein said means for comparing includes second means for storing a correlator output signal representative of the detected state of said pulse pairs.

3. A correlator as set forth in claim 2 wherein said second means for storing is a second flip-flop.

4. A correlator as set forth in claim 3 wherein said means for comparing includes a first AND gate controlled by input signals from one output side of said first-mentioned flip-flop and from said means for receiving, a second AND gate, signal inverter means connected to said means for receiving, said second AND gate being controlled by input signals from said inverter means and from the other side of said first-mentioned flip-flop and a NOR gate controlled by input signals from said first and second AND gates and supplying an input to said second flip-flop.

5. A correlator as set forth in claim 3 wherein said means for comparing includes a first three-input NAND gate controlled by input signals from one output side of said first-mentioned flip-flop, from said means for receiving and from one output side of said second-mentioned flip-flop, a second NAND gate, signal inverter means connected to said means for receiving, said second AND gate being controlled by input signals from said inverter means, from the other output side of said first-mentioned flip-flop and from the other output side of said second-mentioned flip-flop and a third signal gate controlled by input signals from said first and second NAND gates and supplying an input signal to said second-mentioned flip-flop.