Leakage current prevention in semiconductor integrated circuit devices

• US 3,961,358 A
• Filed: 02/21/1973
• Issued: 06/01/1976
• Est. Priority Date: 02/21/1973
• Status: Expired due to Term

• Current Assignee: RCA Corporation (General Electric Company)
• Original Assignee: RCA Corporation (General Electric Company)
• Inventors: Polinsky, Murray Arthur
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US05/334,431
• Time in Patent Office: 1,196 Days
• Field of Search: 317/235 AH, 317/235 AG
• US Class Current: 257/629
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Leakage currents can occur in monolithic semi-conductor integrated circuits through field induced inversion layer channels where the field arises from a layer of distributed charge on the surface of the passivating insulator. These channels can occur at locations where adjacent conductors are at substantially different potentials during circuit operation. At those locations where such channels, if present, could couple a region in the device to another region which may be at some different potential, a conductor layer is disposed on the insulating layer. This conductor layer is adapted to be biased during operation of the device in such a way that an inversion layer channel is not induced thereunder, so that a continuous channel between the two regions cannot be established. Other locations where channels are not likely to occur are left free of conductive material in order to save space.

Claims

1. In a semiconductor integrated circuit device of the type which includes a body of semiconductive material having a surface, regions in said body bounded by PN junctions extending to said surface, a layer of insulating material on said surface, and conductors overlying said layer of insulating material, said conductors, during operation of said device, being at different potentials whereby charge can leak off a conductor and spread over a finite area of said layer of insulating material to act as a field plate to induce an inversion layer channel in said body therebeneath, the improvement comprising:

a conductor layer on said insulating layer over a portion of the finite area of said insulating layer which lies between one of said PN junctions and a conductor from which charge can leak, for preventing such a field induced inversion layer channel from extending into contact with one of said PN junctions,

portions of said insulating layer which do not lie between said PN junction and a conductor from which charge can leak having no conductor layer thereon.

2. The improvement defined in claim 1 in which there are a plurality of said finite areas, and in which there is a conductor layer on said insulating layer over a portion of each of said finite areas.

3. The improvement defined in claim 1 wherein said body has P type regions in N type material, said conductor layer overlying said N type material adjacent to a P type region.

4. The improvement defined in claim 3 wherein said conductor layer is adapted to be coupled to a source of potential during operation of said device.

5. The improvement defined in claim 3 wherein said conductor layer is a portion of a conductor layer which extends into ohmic contact with the adjacent P type region.

6. The improvement defined in claim 5 wherein said conductor layer extends over a portion only of the surface intercept of the PN junction bounding said region.