Low level bio-telemetry system using C/MOS multiplexing

• US 3,962,697 A
• Filed: 06/16/1975
• Issued: 06/08/1976
• Est. Priority Date: 06/16/1975
• Status: Expired due to Term

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Vreeland, Robert
• Primary Examiner(s): Habecker, Thomas B.
• Application Number:
  US05/587,172
• Time in Patent Office: 358 Days
• Field of Search: 340/183, 340/206
• US Class Current: 340/870.14
• CPC Class Codes: A61B 5/0006 ECG or EEG signals
• CPC Class Codes: G08C 15/12 the signals being represented by pulse characteristics in transmission link
• CPC Class Codes: Y10S 128/903 Radio telemetry

Abstract

A low-power, transient-free, multi-channelled bio-telemetry system utilizes series of C/MOS switches coupled to the data sampling electrodes. Shift register pulses selectively enable the switches to sequentially shift the data sample inputs through nine, switch-controlled channels. The switches have little battery drain and, due to their N and P complimentary arrangement, their gating pulses are effectively cancelled and removed from the system channels. Multiplexing precedes amplification by applying switch outputs to a single, low-power amplifier. A special pulse position modulator employing a ramp generator circuit provides the pulse trains to a keyed transmitter. Other significant improvements including a unique shift register arrangement with a synchronizing interval permit long periods of continuous operation undisturbed by the need for battery changes. The transmitted data is received by a suitable demodulating receiver to produce a recordable output for evaluation and computer analysis.

Claims

1. A multi-channel biotelemetry system for multiplexing and transmitting individual data samples derived as signal inputs from a plurality of electrode sources, comprising:

a plurality of complimentary-type MOS switching mechanisms receivably-coupled one to each said data samples, said mechanisms being sequentially operated for cumulatively providing an output pulse train formed of said electrode source samples

broadband main amplifying means receivably coupled to said output pulse train,

pulse-position modulating means receivably-coupled to said amplified train for producing a sequence of output pulses spaced one from another a distance directly proportional to the amplitude of each pulse of said train,

transmitter means coupled to said modulated output,

resetable pulse-generating means for sequentially operating said plurality of switching mechanisms, said means being responsively coupled to said modulated pulse train for generating a separate switch-enabling pulse for each successively-received pulse, and

means for synchronizing the resetting of said pulse-generating means after said switching mechanisms have been sequentially enabled.

2. The system of claim 1 wherein each of said complimentary MOS switching mechanisms includes:

an N-channel switch,

a P-channel switch, and

a circuit coupling said switch-enabling pulses in parallel to said N and P channel switches,

said parallel connections of one of said switches including an inverting means whereby a pulse of one polarity enables one of said switches and an opposite polarity pulse enables the other switch whereby the enabling pulse effectively cancels.

3. The system of claim 1 wherein said pulse position modulating means includes:

a comparator means having a pair of inputs and an output,

a driver amplifier for setting a reference voltage level for the comparator,

said driver amplifier having an input receivably coupled to said amplifying means and an output coupled to one of said comparator inputs so that said reference level of the comparator varies directly with the amplitude of each pulse of said pulse train,

a ramp generator coupled to the other input of said comparator whereby the time required for said generated ramp to reach said comparator level is directly proportional to the amplitude of each pulse of said train,

said comparator producing said pulse position modulated pulses at said reference level,

means for setting the time duration of said comparator output pulse, and

hold-off biasing means for said ramp generator, said comparator output resetting said ramp generator by removing said bias.

4. The system of claim 1 wherein said resettable pulse generating means includes:

a pulse-generating shift register means having a plurality of pulse outputs each coupled to a separate one of said switching mechanisms and a `shift` input responsively coupled to said data sample pulse train, said register shiftably applying a switch-enabling pulse responsively with the receipt of each successive pulse of said train to a successive one of said register outputs,

whereby said switching mechanisms are sequentially enabled to produce said data sample pulse train.

5. The system of claim 4 wherein said shift register further includes:

clock-controlled means for resetting said register after said switching mechanisms have been enabled;

said means being responsive to the coincidence of a final pulse of said pulse train and a clock pulse;

said resetting again applying a switch-enabling pulse to the first of said sequentially-enabled switching mechanisms for initiating a second data sample train, and said coincidence being timed to provide a synchronizing time interval space between successive pulse trains.

6. The system of claim 4 further including:

pulse generating means associated with said shift register means for generating `inhibit` pulse upon the receipt by said register means of said final pulse, said `inhibit` pulse inhibiting transmission of signals to said "shift" input during said synchronizing interval.

7. The system of claim 4 further including:

a pulse-enabled switch means coupled into said system between each of said complimentary MOS switching mechanisms and said main analyzing means for shorting each of said main amplifier during the shifting of said shift register.

8. The system of claim 7 further including:

a second pulse-enabled switch means coupled as a data sample transmission gate into said system between said main amplifying means and said modulating means, said switch means being opened during the shifting of said register means for removing switching transients from said modulation.

9. The system of claim 8 wherein said first and second switch means are complimentary MOS mechanisms including a pair of N and P channel switch members coupled in parallel with each member being activated by a pulse of opposite polarity,

said activating pulses being derived from said pulse train.

10. The system of claim 7 wherein each of said data sample inputs is bipolar and a pair of said sequentially-operated switching mechanisms are provided for each data sample,

said second pulse-enabled switch means being coupled between the outputs of said pair for shorting said pair during said shifting of said register means.

11. The system of claim 10 wherein the second switch means is a complimentary MOS mechanism.