Punchthrough resetting JFET image sensor

• US 3,964,083 A
• Filed: 05/30/1974
• Issued: 06/15/1976
• Est. Priority Date: 06/14/1973
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Lohstroh, Jan
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US05/474,694
• Time in Patent Office: 747 Days
• Field of Search: 357/30, 357/22
• US Class Current: 257/258
• CPC Class Codes: H01L 27/14679 Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
• CPC Class Codes: H01L 31/1126 the device being a field-effect phototransistor

Abstract

A solid-state picture pick-up device according to the invention comprises a number of field effect transistors in which the channel region is bounded by two oppositely located gate electrodes each forming a rectifying junction with the channel region and in which the photosensitive junction is formed by a gate electrode which shows a floating potential. Said gate electrode may be charged by simultaneously applying to the other gate electrode a voltage pulse of a sufficiently large amplitude so that punch-through occurs between the gate electrodes.

Since in this manner each transistor may be adjusted at its own threshold voltage, the influence of the spreading in the threshold voltages on the output signals is considerably reduced.

Claims

1. A semiconductor imaging device, comprising a common semiconductor body comprising an array of plural field effect transistors each having a first gate electrode, a source region and a drain region of one type conductivity adjoining the first gate electrode and defining therebetween a one type conductivity channel region, said first gate electrode comprising a zone of the opposite type conductivity forming a photosensitive p-n junction with the channel region, said first gate zones being electrically floating, some of said field effect transistors having different threshold voltages, and means for electrically charging the first gate zones of each transistor to a reverse potential substantially equal to its threshold voltage producing a depletion region extending from the photosensitive p-n junction in each transistor that just blocks the channel region, whereby the absorption of substantially equal quantities of radiation by each transistor will cause substantially the same change in conduction of its channel.

2. A semiconductor imaging device, comprising a common semiconductor body comprising plural field effect transistors each having a first gate electrode, a source retion and a drain region of one type conductivity adjoining the first gate electrode and defining therebetween a one type conductivity channel region, said first gate electrode comprising a zone of the opposite type conductivity forming a photosensitive p-n junction with the channel region, said first gate zones being electrically floating;

and means for electrically charging said first gate zones to a reverse potential producing a depletion region extending from the photosensitive p-n junction across the channel region, absorption of radiation causing retraction of the depletion region, said first gate charging means comprising for each transistor a second gate electrode located adjoining the channel region so that the latter extends between the first and second gate electrodes and forming a rectifying junction with the channel region and an electrical connection to the second gate electrode for applying a voltage thereto; and

means connected to the source and drain regions of each transistor for deriving an electrical signal indicating the conduction condition of each channel region.

3. A semiconductor device as claimed in claim 2, wherein the said second gate electrodes of the field effect transistors are formed by a semiconductor region of the opposite conductivity type which forms a p-n junction with the channel region of the associated field effect transistor.

4. A semiconductor imaging device as claimed in claim 2 wherein the body comprises a surface-adjoining layer-shaped region of one-type conductivity, said first gate zones being located at least partly in said layer-shaped region, and the second gate electrodes comprise opposite-type surface zones which are laterally separated from each other.

5. A semiconductor device as claimed in claim 4, wherein one of the gate electrodes of the field effect transistors is constituted by an annular surface zone of the opposite conductivity type provided in the layer-shaped region of one conductivity type, the parts of the layer-shaped region, which, viewed on the surface, are enclosed by the annular zones belonging to the source regions or the drain regions of the field effect transistors.

6. A semiconductor device as claimed in claim 4, wherein the said first gate electrodes are each constituted by a surface-adjoining surface zone of the opposite conductivity type, and the said second gate electrodes each comprise a part in the form of a buried zone of the opposite conductivity type which is present in the layer-shaped region and, viewed on the surface, is present below the said surface zone and is connected to the electric connection via a surface-adjoining contact zone of the opposite conductivity type.

7. A semiconductor device as claimed in claim 4, wherein viewed on the surface, the second gate electrode of each field effect transistor formed by a surface zone is present entirely above the first gate electrode of the associated field effect transistor formed by a buried zone, the buried zone extending beyond the edges of the surface zone.

8. A semiconductor device as claimed in claim 7, wherein the area of the part of the buried zone extending beyond the edge of the surface zone is at least half of the overall area of the buried zone.

9. A semiconductor device as claimed in claim 7, wherein the part of the layer-shaped region which is present above the said part of the buried zone extending beyond the edge of the surface zone and extending from the buried zone up to the surface shows a lower doping concentration than the said surface zone.

10. A semiconductor imaging device as claimed in claim 2 wherein the first gate charging means includes means for applying to the second gate electrical connection a pulsed voltage exceeding the punchthrough voltage between the first and second gate electrodes, the first gate retaining its charge in the absence of incident radiation when the pulsed voltage terminates.

11. A semiconductor device as claimed in claim 10, wherein the voltage to be applied to the said second gate electrode is at least equal to twice the punchthrough punch-through voltage between the said first and second gate electrodes.

12. A semiconductor imaging device as claimed in claim 10 and further including means for maintaining a reverse bias potential on the second gate subsequent to charging of the first gate during a storage interval and means for reducing the reverse bias potential on the second gate during a readout interval.

13. A semiconductor device as claimed in claim 12, wherein the applied reverse bias across the p-n junction between the second gate electrode and the associated channel region is at least equal to the punch-through voltage between the second gate electrode and the first gate electrode in the relevant field effect transistor.