Diffusion guarded metal-oxide-silicon field effect transistors

• US 3,967,988 A
• Filed: 03/14/1975
• Issued: 07/06/1976
• Est. Priority Date: 08/05/1974
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Davidsohn, Uryon S.
• Primary Examiner(s): Rutledge, L. Dewayne
• Assistant Examiner(s): Davis, J.
• Application Number:
  US05/558,592
• Time in Patent Office: 480 Days
• Field of Search: 148/187, 29/571, 357/23, 357/41, 357/89
• US Class Current: 438/279
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00

Abstract

Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.

Claims

1. A method for fabricating a field effect transistor having at least one guard region in a semiconductor substrate of one conductivity type, which comprises:

forming spaced apart source and drain regions of opposite conductivity type to said substrate in said substrate,

forming an insulating layer over the space between said source and drain regions,

forming a conductive gate electrode having two ends over said insulating layer, and

subsequently forming said at least one guard region so that the ends of said gate electrode are in registration with a corresponding portion of said at least one guard region.

2. The method of claim 1 in which said insulating layer is silicon dioxide and said gate electrode is silicon.

3. The method of claim 2 in which said source region extends around said drain region and a separate guard region is diffused at each end of said gate electrode.

4. The method of claim 1 in which said source region extends around said drain region and a separate guard region is diffused at each end of said gate electrode.