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Dynamic random access memory misfet integrated circuit

  • US 3,969,706 A
  • Filed: 10/08/1974
  • Issued: 07/13/1976
  • Est. Priority Date: 10/08/1974
  • Status: Expired due to Term
First Claim
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1. The random access memory which comprises a monolithic semiconductor chip having formed thereon:

  • a matrix of memory cells each including a data storage capacitor, the cells being arrayed in rows and columns, the storage capacitor of each cell in each column being connected to a corresponding column bus in response to a voltage on a row address line and the data being transferred to and from each cell in each column by the corresponding column bus;

    a sense amp for each column bus for discriminating between at least two voltage levels representative of logic states and storing the detected logic state;

    a plurality of address inputs;

    row address latch means for storing address data applied to the address inputs;

    row decoder means for enabling a row address line designated by the address data in the row address latch means;

    a row address strobe signal input;

    row address clock and control means responsive to a signal on the row address strobe input for automatically causing the data on the address inputs to be latched in the row address latch means, for causing a row address line to enable the storage cells in the row, and for causing the data in the storage cells to be transferred by the respective column buses to the respective sense amp and stored, and for rewritting data from the respective column buses into the respective cells;

    a column address strobe signal input;

    column address latch means for storing address data applied to said address inputs;

    a data bus;

    column decoder means for enabling an addressed sense amp to transfer data between the data bus and the enabled sense amp;

    a data input;

    a data input latch for storing data applied to the data input;

    a data output;

    a data output latch for storing at least two logic levels and applying corresponding logic signals to the data output;

    a chip select signal input;

    a write signal input; and

    column clock and control means responsive to a signal on the column address strobe for latching data applied to the address line in the column address latch means, and in the presence of a predetermined signal on the chip select input for enabling an addressed sense amp to transfer data from the sense amp through the data bus to the data output latch, and in the presence of a predetermined signal on the chip select input and on the write input for latching data applied to the data input in the data input latch and transferring data from the data input latch to the enabled sense amp while isolating the data output latch from the data bus.

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