Dynamic random access memory misfet integrated circuit

• US 3,969,706 A
• Filed: 10/08/1974
• Issued: 07/13/1976
• Est. Priority Date: 10/08/1974
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Rtx Corporation)
• Inventors: Green, Robert Sherman, Proebsting, Robert James
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US05/513,091
• Time in Patent Office: 644 Days
• Field of Search: 340/173 R, 340/172.5, 307/238
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits

Abstract

A MISFET dynamic random access memory chip having 4,096 single transistor, single capacitor storage cells yet packaged in a standard sixteen pin dual inline package is disclosed. Six bit row address and six bit column address data are sequentially multiplexed into row address latches and column address latches through six address pins by sequentially occurring row address and column address strobes. Sixty-four bits of information from an address row are read and transferred to a sixty-four bit column register. One bit of the column register is then selected by the column address decoder so that data is transferred from that bit to a data output latch. Data is transferred into a data input latch and then to the addressed bit of the storage matrix as well as to the addressed column register by a write signal. Upon completion of the row address strobe cycle, each cell in the address row is automatically refreshed by the data in the respective bit of the column register, including the bit which may have been modified by a write cycle. The state of the data output latch remains valid until a subsequent column address strobe is received. The write signal to the chip provides for a read only or a write only cycle, in addition to the read-modify-write cycle. In the absence of a chip select, the data output assumes an open circuit condition. The sense amp utilizes a dynamic differential amplifier to sense a voltage change of a precharged column bus. The entire system is substantially entirely dynamic in operation and accordingly has very low power consumption.

Claims

1. The random access memory which comprises a monolithic semiconductor chip having formed thereon:

a matrix of memory cells each including a data storage capacitor, the cells being arrayed in rows and columns, the storage capacitor of each cell in each column being connected to a corresponding column bus in response to a voltage on a row address line and the data being transferred to and from each cell in each column by the corresponding column bus;

a sense amp for each column bus for discriminating between at least two voltage levels representative of logic states and storing the detected logic state;

a plurality of address inputs;

row address latch means for storing address data applied to the address inputs;

row decoder means for enabling a row address line designated by the address data in the row address latch means;

a row address strobe signal input;

row address clock and control means responsive to a signal on the row address strobe input for automatically causing the data on the address inputs to be latched in the row address latch means, for causing a row address line to enable the storage cells in the row, and for causing the data in the storage cells to be transferred by the respective column buses to the respective sense amp and stored, and for rewritting data from the respective column buses into the respective cells;

a column address strobe signal input;

column address latch means for storing address data applied to said address inputs;

a data bus;

column decoder means for enabling an addressed sense amp to transfer data between the data bus and the enabled sense amp;

a data input;

a data input latch for storing data applied to the data input;

a data output;

a data output latch for storing at least two logic levels and applying corresponding logic signals to the data output;

a chip select signal input;

a write signal input; and

column clock and control means responsive to a signal on the column address strobe for latching data applied to the address line in the column address latch means, and in the presence of a predetermined signal on the chip select input for enabling an addressed sense amp to transfer data from the sense amp through the data bus to the data output latch, and in the presence of a predetermined signal on the chip select input and on the write input for latching data applied to the data input in the data input latch and transferring data from the data input latch to the enabled sense amp while isolating the data output latch from the data bus.

2. The random access memory of claim 1 wherein each sense amp comprises:

a differential amplifier having reference and data input nodes, the amplifier being adapted to output one logic signal when the inputs are near the same voltage and another logic level when the inputs are at different voltage levels, and means responsive to the row clock and control means for precharging the respective column bus to a reference voltage level and trapping the reference voltage on the reference input node, and then outputting a logic level dependent upon the voltage level of the respective column bus after the respective addressed memory cell is enabled.

3. The random access memory which comprises a monolithic semiconductor chip having formed thereon:

a matrix of storage cells arrayed in rows and columns, the storage cell in each column being connected to a corresponding column bus in response to a voltage on a row address line and the data being transferred to and from each cell in each column by the corresponding column bus;

a sense amp for each column bus for detecting the logic state of an enabled cell connected to the respective column bus as the cell is enabled and holding the detected logic state;

row address means for enabling a row of storage cells designated by row address data;

a row address strobe input for inputting a row address strobe signal to the chip;

row address clock and control means responsive to a row address strobe signal on the row address strobe input for automatically causing an addressed row of storage cells to be enabled and the data in the storage cells of the row to be detected by the respective sense amp and held;

a data bus;

column address means responsive to a column address strobe signal input to the chip after the row address strobe signal for enabling an addressed sense amp to transfer data between the data bus and the enabled sense amp; and

data transfer means for transferring data between the data bus and circuitry external to the chip.

4. In a random access memory which comprises a monolithic semiconductor chip having a matrix of storage cells arrayed in rows and columns, the method of addressing a storage cell which comprises applying a first set of binary address signals to a number of address inputs to the chip and then applying a second set of address signals to the same address inputs to specifically identify a selected column of the array and thus identify a selected cell.

5. The method of addressing a desired memory cell of a memory formed on a monolithic semiconductor chip having a matrix of storage cells arrayed in rows and columns which comprises sequentially applying first and second sets of binary address signals to the same address inputs to the chip to identify the row and column of the desired memory cell.

6. In a random access memory formed on a monolithic semiconductor chip and having a series of precharge periods each followed by a data access period initiated by a strobe signal, the method for outputting data from the chip which comprises reading data from a selected memory cell during an access period and storing the data read from the cell in a data output latch during the remainder of the access period and at least a portion of the succeeding precharge period, and outputting the data from the data output latch to circuitry external of the chip during at least a portion of said succeeding precharge period.

7. The circuit for producing a clock signal above a drain supply voltage between first and second successive clock edges and substantially at a source supply voltage after the second clock edge until a precharge signal which occurs some period after the second clock edge and terminates before the next first clock edge which comprises:

a precharge node,

an output node,

a capacitor coupling the precharge node and the output node,

a first transistor connecting the precharge node to the drain supply voltage,

a second transistor connecting the precharge node to the source supply voltage,

a third transistor connecting the output node to the drain supply voltage, and

a fourth transistor connecting the output node to the source supply voltage,

the second and third transistors being turned on by the precharge signal, the first transistor being turned on by the first clock edge and the fourth transistor being turned off by the second clock edge.

8. In a random access memory formed on a monolithic semiconductor chip and having a plurality of memory cells each having a storage capacitor connected to a column bus when a transistor is turned on by an enabling signal, the method of detecting the logic level stored on the capacitor of an enabled cell which comprises:

precharging the column bus to precharge voltage level,

sampling the precharge voltage level on the column bus and storing the sampled voltage on a reference node,

then enabling a selected storage cell by turning the transistor of the selected cell on,

detecting a predetermined change in the column bus from the sampled voltage stored on the reference voltage, and

changing the voltage level on the column bus in the event a predetermined change in the voltage level is detected, to a voltage level corresponding to the voltage level of the capacitor of the enable cell before the cell was enabled.

9. In a random access memory, the method of claim 8 wherein:

the column bus is precharged to a voltage near a drain supply voltage, and

the column bus is discharged to a voltage level near a source supply voltage in the event a predetermined charge in the voltage of the column bus is detected by turning a transistor on to connect the column bus to a source supply voltage.

10. In a random access memory, the sense amp for detecting voltage levels on a column bus connected to a memory cell by row enabling signal comprising:

a differential amplifier having reference and data input nodes connectable to the column bus, the amplifier being adapted to output, when enabled, one logic state when the input nodes are near the same voltage level and another logic state when the inputs are at different voltage levels, and

circuit means for precharging the column bus and the reference node to a precharge level, then isolating the precharge node from the column bus and connecting a memory cell to the column bus to change the voltage level of the column bus if said other logic state is stored in the memory cell without changing the voltage level on the reference node, and then enabling the output of the amplifier.

11. In a random access memory formed on a monolithic chip and having a plurality of memory cells arrayed in rows and columns, the method of accessing data which comprises:

applying a row strobe to the chip to automatically transfer data from all memory cells in an addressed row to a column register, and applying a column strobe to the chip to automatically transfer data between an addressed bit of the column register and circuitry external to the chip, the row address data and column address data being substantially input to the chip through the same address inputs to the chip.

12. In a random access memory which comprises a monolithic semiconductor chip, the combination of:

a matrix of storage cells arrayed in rows and columns, the storage cell in each column being connected to a corresponding column bus in response to a voltage on a row address line and data being transferred to and from each cell in each column by the corresponding column bus;

sense amp means for each column bus for discriminating between at least two voltage levels representative of logic states and holding the detected logic state;

a plurality of binary row address inputs to the chip sufficient in number to binarily define the number of rows or columns, whichever is greater;

a row address strobe input for inputting a row address strobe to the chip;

row address decode means responsive to a row address strobe input to the chip for decoding row address data and holding the addressed row of memory cells enabled until termination of the row address cycle;

a column address strobe input for inputting a column address strobe signal to the chip;

column address latch means for storing column address data applied to said address inputs; and

column address decoder means responsive to a column address strobe signal for enabling the transfer of data from the sense amp means for the column identified by the column address.

13. In a random access memory which comprises a monolithic semiconductor chip, the combination of:

a matrix of storage cells arrayed in rows and columns;

a plurality of address inputs limited in number to that required to define the greater of the number of rows or columns for inputting a corresponding number of address signals to the chip;

strobe input means for inputting time spaced row address strobe and column address strobe signal to the chip;

row address means responsive to a row address strobe input through the strobe input means for holding a row of storage cells defined by the address signals then on the address inputs enabled for processing of data therein; and

column address means responsive to a column address strobe input through the strobe input means for holding the storage cells defined by the address signals then on the address inputs enabled for processing of data therein.

14. The combination of Claim 13 further characterized by means for automatically in response to a row address strobe and independent of the column address strobe refreshing data stored in all memory cells in the row defined by the address signals then on the address inputs.

15. The method of addressing a selected memory cell of a matrix of memory cells arrayed in rows and columns on a monolithic semiconductor chip disposed in a multiple pin package which comprises:

applying one binary input of a set of binary inputs which identify the row of selected memory cell to each of a set of address pins of the package;

applying one address strobe signal to a pin of the package to cause the row address information on the set of address pins to be input and stored in the circuit;

then

applying each binary input of a set of binary inputs which identify the column of the selected memory to one of the same set of address pins of the package; and

applying another address strobe signal to a pin of the package to cause to column address information on the set of address pins to be input to the circuit.

16. In a memory formed on a monolithic semiconductor chip of a field effect transistor and having a plurality of logic inputs to which logic input signals are normally applied in sequence in the operation of the memory, the input circuit comprising an inverter stage including:

an output node for the inverter stage;

a load impedance circuit including an impedance device and a first transistor connecting the output node to a drain voltage supply node so as to block any current through the impedance circuit when turned off; and

an input circuit including at least a second transistor connecting the output node to a source supply voltage node, the gate of the second transistor being a logic input to the chip;

the first transistor being turned on in response to a logic input signal normally applied to another logic input to the chip before a logic signal would normally be applied to the gate of the second transistor whereby the inverter stage will be turned off and not dissipate energy in the absence of the earlier logic signal.

17. In a random access memory formed on a monolithic semiconductor chip having a matrix of memory cells and logic means for addressing a selected memory cell of the matrix, the combination of

strobe input means for inputting an externally generated strobe signal to the chip;

first means for applying externally generated alternative logic levels to the chip for indicating that the chip is selected or not selected;

second means for applying externally generated alternative logic levels to the chip for indicating a read cycle or a write cycle; and

logic means responsive to an externally generated strobe signal applied to the strobe input means including data output latch means for;

a. in the presense of a chip not selected logic level on the first means causing the data output to be an open circuit until responding to another strobe input signal,

b. in the presence of a chip selected logic level on the first means and a read cycle logic level on the second means producing a logic output representative of the logic level stored in an addressed memory cell until responding to another strobe input signal, and

c. in the presence of a chip selected logic level and a write logic level automatically storing data in an addressed memory cell and a predetermined state at the data output until responding to another strobe input signal.

18. In a random address memory formed on a monolithic chip and having a matrix of memory cells arrayed in rows and columns, a set of address inputs sufficient in number to logically define only the number of rows or columns, whichever is greater, strobe input means for sequentially inputting a row strobe signal and a column strobe signal to the chip, data means for inputting and outputting binary data from the chip, and read/write control input means for inputting a signal to the chip having a read logic strobe for a read common and write logic strobe for a write command, the method comprising:

applying a set row address signals representing a row of memory cells in the matrix to the address inputs to the chip;

gating the row address signals into the chip in response to a row strobe signal and then holding the row of memory cells identified by the row address signals enabled;

applying a set of column address signals representing a column of memory cells in the matrix to the same address inputs to the chip; and

gating the column address signals into the chip in response to a column strobe signal to enable the processing of data in the memory cell of the addressed row and the addressed column.

19. The method of claim 18 further comprising:

applying a succession of sets of column address signals to the address inputs and a succession of column strobe signals to the strobe input means while holding the same row of memory cells enabled to sequentially enable the processing of data in a series of enabled memory cells in the addressed row.

20. The method of claim 18 wherein the write logic state is applied to the read/write control input means before said predetermined minimum time after the column strobe signal of automatically causing the data output from the chip to go to an open circuit and to automatically cause data at a data input to the chip to be stored in the addressed memory cell.

21. The method of claim 18 further comprising:

applying said read logic state to the read/write control input means for a predetermined minimum time before and after the column strobe signal for automatically causing data in the addressed memory cell to be stored in a data output latch and be output from the chip until after the next input on the strobe input means.

22. The method of claim 21 further comprising changing the logic state applied to the read/write control input means from the read logic state to the write logic state after the predetermined minimum time after the column strobe signal for automatically causing data to be input and stored in the addressed memory cell while the data read from the addressed memory cell continues to be stored in the data output latch.

23. In a random address memory formed on a monolithic chip and having a plurality of memory cells arrayed in rows and columns, the method of accessing data which comprises:

applying a row strobe signal to the chip to automatically transfer data from all memory cells in an addressed row to a column register, and applying a column strobe signal to the chip to then automatically transfer data between an addressed bit of the column register and circuitry external to the chip.

24. The method of claim 23 wherein a write signal is gated into the chip by the column strobe signal to cause the automatic transfer of data at a data input to the addressed memory cell.

25. The method of claim 24 wherein the data output is caused to go to a predetermined logic state in the event a write signal is applied to the chip before or within a predetermined time period after a column strobe signal is applied to the chip.

26. The method of claim 23 wherein the absence of a write signal applied to the chip at the time of the column strobe signal results in data from an addressed bit of the column register being automatically output from the chip in response to a column strobe signal.

27. The method of claim 26 wherein a write signal applied to the chip a predetermined period of time after a column strobe signal is applied to the chip automatically transfers data at a data input to an addressed memory cell after data is output from the addressed bit of the column register.

28. The method of claim 26 wherein the transfer of data to or from the chip enabled by a chip select signal is disabled by the absence of a chip select signal applied to the chip.

29. The method of claim 28 further characterized by causing:

the data output to go to an open circuit condition in the absence of a chip select signal.

30. The method of claim 23 wherein a plurality of sets of addresses and column strobes are sequentially applied to the chip after a single row strobe to automatically sequentially transfer data between a plurality of bits of the column register and circuitry external to the chip.