Wireless burglar alarm system

• US 3,969,709 A
• Filed: 06/26/1969
• Issued: 07/13/1976
• Est. Priority Date: 06/26/1969
• Status: Expired due to Term

• Current Assignee: Albert Stern, Roger Isaacs
• Original Assignee: Albert Stern, Roger Isaacs
• Inventors: Stern, Albert, Isaacs, Roger
• Primary Examiner(s): Trafton, David L.
• Application Number:
  US04/836,848
• Time in Patent Office: 2,574 Days
• Field of Search: 340/224, 340/216, 340/416, 325/57, 343/228
• US Class Current: 340/502
• CPC Class Codes: G08B 13/22 Electrical actuation

Abstract

A radio intrusion alarm system utilizing a high frequency carrier signal having an audio subcarrier which may be modulated by two tone signals, the first tone signal causing actuation of an alarm, the second tone signal causing actuation of a time delay means which inhibits operation of the alarm to permit an authorized entry, for example, at the transmitter location without giving the alarm.

Claims

1. A wireless burglar alarm system comprising

a wireless transmitter, and

a receiver,

a first output circuit connected to said receiver and responsive to a first predetermined frequency,

a second output circuit connected to said receiver and responsive to a second predetermined frequency,

warning means connected to said second output circuit as a load thereof,

said first output circuit being connected to said second output circuit,

said transmitter being selectively operable to transmit signals having one of said first and second predetermined frequencies,

said receiver being operable upon the reception of an input signal from said transmitter to produce an output signal having one of said first and second predetermined frequencies,

said second output circuit being selectively operable upon the application of said output signal from said receiver at said second predetermined frequency to activate said warning means, and

said first output circuit being operable upon the application of said output signal from said receiver at said first predetermined frequency to inhibit the operation of said second output circuit and said warning means.

2. A wireless burglar alarm system in accordance with claim 1, wherein

said first output circuit includes means to inhibit the operation of said second output circuit for a predetermined period of time within which period of time said second output circuit is ineffective to activate said warning means upon the application of said second predetermined frequency signal to said second output circuit.

3. A wireless burglar alarm system in accordance with claim 2, wherein

said transmitter is operable to transmit and said receiver is operable to receive a double modulated rf carrier signal having a low frequency modulating signal, and

said receiver is operable to demodulate said carrier signal to produce said low frequency signal as the output signal thereof.

4. A wireless burglar alarm system in accordance with claim 3, wherein

said double modulated signal comprises an rf carrier wave component, a mid-range audio frequency component and a low frequency component, and wherein

said receiver includes means to demodulate said double modulated rf carrier signal to produce said low frequency component as the sole output signal thereof.

5. A wireless burglar alarm system in accordance with claim 2, wherein

said warning means is an audible warning device.

6. A wireless burglar alarm system in accordance with claim 5, wherein

said second output circuit includes selectively operated switch means to deactivate said audible warning device after activation thereof.

7. A wireless burglar alarm system in accordance with claim 1, wherein

said second output circuit comprises

an input stage, and

an output stage,

said warning means being connected as a load to said output stage, and

said input stage including frequency selective means to pass to said output stage substantially only those output signals from said receiver whose frequency is said second predetermined frequency.

8. A wireless burglar alarm system in accordance with claim 7, wherein

said input stage includes

a first transistor having first, second and third terminals,

a transformer having primary and secondary coils, and

a potential source,

said second and third terminals being adapted to have said receiver output signal applied thereacross and to produce a transistor output signal across said first and third terminals,

said frequency selective means including said transformer,

said primary coil being connected between said potential source and said first terminal,

said frequency selective means also including a capacitor connected in parallel across said primary coil and forming therewith a resonant circuit tuned to said second predetermined frequency, and

means for connecting said secondary coil to said output stage.

9. A wireless burglar alarm system in accordance with claim 8, including

a second capacitor connected in parallel across said secondary coil and forming therewith a second resonant circuit tuned to said second predetermined frequency, and

said first resonant circuit and said second resonant circuit comprising said frequency selective means.

10. A wireless burglar alarm system in accordance with claim 9, wherein

said first transistor terminal is the collector,

said second transistor terminal is the base, and

said third transistor terminal is the emitter.

11. A wireless burglar alarm system in accordance with claim 10, wherein

said warning means is activated when said second output circuit is in an activated condition and inactivated when said second output circuit is in its inactivated position.

12. A wireless burglar alarm system in accordance with claim 11, wherein

said first output circuit comprises

an input stage, and

an output stage,

means connecting said output stage of said first output circuit to said output stage of said second output circuit, and

said last mentioned input stage including frequency selective means to pass to said output stage of said first output circuit substantially only those output signals from said receiver whose frequency is said first predetermined frequency.

13. A wireless burglar alarm system in accordance with claim 12, wherein

said last mentioned input stage includes

a second transistor having first, second and third terminals,

a second transformer having a second primary and a second secondary coil, and

a second potential source,

said second and third terminals being adapted to have said receiver output signal applied thereacross and to produce a transistor output signal across said first and third terminals,

said second primary coil being connected between said second potential source and said first terminal,

said frequency selective means comprising said second primary coil and a second capacitor connected in parallel across said second primary coil and forming therewith a resonant circuit tuned to said first predetermined frequency, and

means for connecting said second secondary coil to said output stage.

14. A receiver circuit assembly for use with burglar alarm systems, said assembly comprising

a receiver,

a first output circuit connected to said receiver and responsive to a first predetermined frequency,

a second output circuit connected to said receiver and responsive to a second predetermined frequency,

warning means connected to said second output circuit as the load thereof,

said receiver being operable to produce an output signal having one of said first and second predetermined frequencies upon the reception of an input signal thereto,

said first output circuit being connected to said second output circuit,

said second output circuit being selectively operable upon the application of said output signal from said receiver at said second predetermined frequency to activate said warning means,

said first output circuit being operable upon the application of said output signal from said receiver at said first predetermined frequency to inhibit the operation of said second output circuit and said warning means,

said second output circuit comprising

an input stage, and

an output stage,

said warning means being connected as a load to said output stage,

said input stage including frequency selective means to pass to said output stage substantially only those output signals from said receiver whose frequency is said second predetermined frequency,

said output stage having an activated and an inactivated condition and said warning means being activated when said output stage is in its activated condition and inactivated when said output stage is in its inactivated condition,

said output stage comprising

a triggering device,

a trigger activating switch, and

a load activating switch,

means connecting said input stage to said trigger activating switch,

means connecting said trigger activating switch to said triggering device,

means connecting said triggering device to said load activating device,

means connecting said load activating device to said load,

said trigger activating switch being adapted to be actuated upon the application of an output signal from said input stage at said second predetermined frequency, and

actuation of said trigger activating switch actuating said triggering device and said load activating switch to thereby activate said load.

15. A receiver circuit assembly in accordance with claim 14, wherein

said trigger activating switch includes

a first transistor having first, second and third terminals, and

a potential source,

said potential source being connected to said first terminal,

said second and third terminals being adapted to have the output signal from said input stage applied thereacross and to produce an output signal across said first and third terminals when said input stage output signal is at said second predetermined frequency.

16. A receiver circuit assembly in accordance with claim 15, wherein

said triggering device is an SCR comprising

an anode,

a cathode, and

a gate,

a voltage source connected to said anode,

said means connecting said trigger activating switch to said triggering device comprising a relay including

a coil, and

a pair of normally open contacts,

said coil being connected between said potential source and the first terminal of said first transistor, and

said normally open contacts being connected between said voltage source and said gate, whereby when said transistor conducts said normally open contacts are closed to cause current flow to the gate of said SCR causing the same to fire.

17. A receiver circuit assembly in accordance with claim 16, wherein

said load activating switch comprises a second relay including

a second coil, and

at least a pair of normally open contacts,

said second relay coil being connected between said cathode and a ground terminal, and

said last mentioned normally open contacts being effectively connected between said load and one terminal of said voltage source, whereby firing of said SCR causes current flow through said second relay coil causing said last mentioned normally open contacts to close to thereby connect said voltage source across said load and activate the same.

18. A receiver circuit assembly in accordance with claim 17, wherein

said output stage includes selectively operable switch means connected to said load for selectively deactivating said load after activation thereof.

19. A receiver circuit assembly in accordance with claim 18, wherein

said selectively operable switch means comprises a keyswitch.

20. A receiver circuit assembly in accordance with claim 19, wherein

said keyswitch is connected to said voltage source and is operable to disconnect said voltage source from said load and said SCR.

21. A receiver circuit assembly in accordance with claim 17, wherein

said warning means comprises an audible warning device.

22. A receiver circuit assembly in accordance with claim 17, wherein

said output stage includes a third relay comprising

a third coil, and

a pair of normally closed contacts,

said coil being effectively connected to said potential source,

said last mentioned normally closed contacts being connected in parallel across said normally open contacts of said first relay,

said last mentioned normally closed contacts being maintained in an open condition by the flow of current from said potential source through said third coil and returning to said normally closed position upon the cessation of current flow through said third coil, thereby firing said SCR and activating said load.

23. A receiver circuit assembly in accordance with claim 20, wherein

said first transistor terminal is the collector,

said second transistor terminal is the base, and

said third transistor terminal is the emitter.

24. a receiver circuit assembly in accordance with claim 17, wherein

said input stage includes

a second transistor having first, second and third terminals,

a transformer having primary and secondary coils, and

a second potential source,

said second and third terminals being adapted to have said receiver output signal applied thereacross and to produce a transistor output signal across said first and third terminals,

said frequency selective means including said transformer,

said primary coil being connected between said second potential source and said first terminal,

said frequency selective means also including a capacitor connected in parallel across said primary coil and forming therewith a resonant circuit tuned to said second predetermined frequency, and

means for connecting said secondary coil to said output stage.

25. A receiver circuit assembly in accordance with claim 24, including

a second capacitor connected in parallel across said secondary coil and forming therewith a second resonant circuit tuned to said second predetermined frequency, and

said first resonant circuit and said second resonant circuit comprising said frequency selective means.

26. A receiver circuit assembly in accordance with claim 25, wherein

said first transistor terminal is the collector,

said second transistor terminal is the base, and

said third transistor terminal is the emitter.

27. A receiver circuit assembly in accordance with claim 25, wherein

said first output circuit comprises

an input stage, and

an output stage,

said output stage comprises

a second triggering device,

a second trigger activating switch, and

an inhibiting switch means,

means connecting said input stage to said second trigger activating switch,

means connecting said second trigger activating switch to said second triggering device,

means connecting said second triggering device to said inhibiting switch means, and

means connecting said inhibiting switch means to said second output stage,

said second trigger activating switch being adapted to be actuated upon the application of an output signal from said input stage and said first predetermined frequency, and

actuation of said second trigger activating switch actuating said second triggering device and said inhibiting switch means to thereby inhibit said second output stage and maintain the same in an inactivated condition.

28. A receiver circuit assembly in accordance with Claim 27, wherein

said first output stage includes a timing circuit,

means connecting said timing circuit to said second triggering device, and

said timing circuit being operative upon the actuation of said second triggering device to commence its timing cycle and operative upon the completion of its timing cycle to deactuate said second triggering device and said inhibiting switch means to thereby uninhibit said second output stage.

29. A receiver circuit assembly in accordance with Claim 28, wherein

said timing circuit is reset to commence its timing cycle upon the application of another signal to said second trigger activating switch during said initial timing cycle and prior to the completion thereof so as to maintain said second output stage in its inhibited and inactivated condition.

30. A receiver circuit assembly in accordance with Claim 28, wherein

said second trigger activating switch includes

a third transistor having first, second and third terminals, and

a third potential source,

said third potential source being connected to said first terminal,

said second and third terminals being adapted to have the output signal from said input stage applied thereacross and to produce an output signal across said first and third terminals when said input stage output signal is at said first predetermined frequency.

31. A receiver circuit assembly in accordance with Claim 30, wherein

said second triggering device is a second SCR comprising

a second anode,

a second cathode, and

a second gate,

a second voltage source connected to said second anode,

said means connecting said second trigger activating switch to said second triggering device comprising a fourth relay including

a fourth coil, and

a pair of normally closed contacts,

said fourth coil being connected between said third potential source and the first terminal of said third transistor.

32. A receiver circuit assembly in accordance with Claim 31, wherein

said inhibiting switch means comprises a fifth relay including

a fifth coil, and

a pair of normally closed contacts,

said fifth relay coil being effectively connected between said second cathode and a ground terminal,

said normally closed contacts of said fifth relay being connected to said first trigger activating switch, whereby firing of said second SCR causes current flow through said fifth relay coil causing said normally closed contacts of said fifth relay to open to thereby inhibit said first trigger activating switch and maintaining the output stage of said second output circuit and said warning means in an inactivated condition.

33. A receiver circuit assembly in accordance with Claim 32, wherein

said normally closed contacts of said fifth relay are connected between said third terminal of said first transistor and ground.

34. A receiver circuit assembly in accordance with Claim 33, wherein

said timing circuit is connected between the second cathode of said second SCR and a ground terminal, and

said timing circuit is operable upon the firing of said second SCR to commence its timing cycle and operative upon completion of its timing cycle to cause said second SCR to cease conducting and to thereby return said second output circuit to its uninhibited condition.

35. A receiver circuit assembly in accordance with Claim 34, wherein

said timing circuit is reset to commence its timing cycle upon the application of another signal to the second gate of said second SCR during said initial timing cycle and prior to the completion thereof so as to maintain said second output stage in its inhibited and inactivated condition.

36. A receiver circuit assembly in accordance with Claim 35, wherein

said fourth relay includes a pair of normally opened contacts,

said normally opened and normally closed contacts of said fourth relay having a common junction therebetween connected to one of each of said pairs of contacts and to a ground terminal,

said timing circuit comprising

a unijunction transistor having

an emitter,

a first base, and

a second base,

a first series connected resistance-capacitance circuit, and

a second series connected resistance-capacitance circuit,

said first resistance-capacitance circuit being connected between the second cathode of said second SCR and a ground terminal with the resistance being connected to said second SCR cathode and said capacitance being connected to ground,

the junction between said last mentioned resistance and said last mentioned capacitance being connected to said first base, and

a resistor connected between said second base and said second SCR cathode.

37. A receiver circuit assembly in accordance with Claim 32, wherein

said second relay includes

a pair of normally closed contacts, and

said last mentioned normally closed contacts being connected between one terminal of said fifth relay coil and said ground terminal.

38. A receiver circuit assembly in accordance with Claim 32, wherein

said receiver is adapted to receive a double modulated carrier signal having a high frequency component, a midfrequency component and a low frequency component,

said receiver comprising

an input stage,

a first intermediate stage,

a second intermediate stage, and

an output stage,

first means connecting said first intermediate stage to said input stage,

second means connecting said input stage to said first intermediate stage,

third means connecting said input stage to said second intermediate stage,

fourth means connecting said second intermediate stage to said output stage,

said input stage including frequency selective means tuned to said high frequency component of said double modulated carrier signal,

said input stage being adapted to pass to said first intermediate stage said double modulated carrier signal,

said first intermediate stage being operable upon the reception of said double modulated carrier signal to produce an output signal,

said first means connecting said first intermediate stage to said input stage including

means to prevent the passage therethrough of said high frequency component, thereby demodulating said double modulated carrier signal and presenting a single modulated carrier signal to said input stage,

said input stage being operable upon the reception of said single modulated carrier signal to produce an output signal which is passed to said second intermediate stage through said third connecting means, and thence to said output stage through said fourth connecting means, and

said output stage including means to demodulate said single modulated carrier signal, thereby producing said low frequency component as the output signal thereof.

39. A receiver circuit assembly in accordance with Claim 38, wherein

said first intermediate stage is operable to amplify the input signal applied thereto.

40. A receiver circuit assembly in accordance with Claim 39, wherein

said third means includes blocking means to prohibit the passage of said double modulated carrier signal from said input stage to said second intermediate stage.

41. A receiver circuit assembly in accordance with Claim 40, wherein

said first intermediate stage comprises an oscillator having an output tank tuned to the frequency of said high frequency component of said carrier wave, and

said second means is connected from the output of said input stage to said tuned tank.

42. A receiver circuit assembly in accordance with Claim 41, wherein

said first means is interconnected between the output of said oscillator and said input stage and includes

a choke, and

a bypass capacitor,

said bypass capacitor having one terminal thereof connected to said choke and the other terminal thereof connected to ground.

43. A receiver circuit assembly in accordance with claim 42, wherein

said fourth means includes

a waveshaping network, and

a frequency selective network, and

said frequency selective network being tuned to said mid-frequency to permit the passage therethrough of said single modulated carrier signal at said mid-frequency.

44. A receiver circuit assembly in accordance with Claim 43, wherein

said frequency selective network comprises

an inductor and

a capacitor,

said inductor and said capacitor being connected in series and forming a series tuned network.

45. A receiver circuit assembly in accordance with Claim 44, wherein

said input stage includes a fourth transistor having first, second and third terminals,

said second and third terminals being adapted to have said double modulated carrier signal applied thereacross and to produce an output signal across said first and second terminals, and

said last mentioned output signal being applied to the tuned tank of said oscillator through said second means.

46. A receiver circuit assembly in accordance with claim 45, wherein

said oscillator output is fed through said first means and applied across said second and third terminals of said fourth transistor to produce an output signal across said first and third terminals thereof, and

said last mentioned output signal being fed to said second intermediate stage through said third means.

47. A receiver circuit assembly in accordance with Claim 46, wherein

said first transistor terminal is the collector,

said second transistor terminal is the base, and

said third transistor terminal is the emitter.

48. A receiver circuit assembly in accordance with Claim 47, wherein

said frequency selective means comprises

a second inductor, and

a second capacitor,

said second inductor and said second capacitor being connected in parallel between said emitter and a ground terminal.

49. A receiver circuit assembly in accordance with Claim 48, wherein

said blocking means of said third means comprises

a second choke, and

a second bypass capacitor,

said second choke being connected between said collector and said second intermediate stage, and

said second bypass capacitor being connected between the terminal of said second choke remote from said collector and ground.