Vertical multijunction solar cell

• US 3,969,746 A
• Filed: 12/10/1973
• Issued: 07/13/1976
• Est. Priority Date: 12/10/1973
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Matzen, Walter Theodore, Kendall, Don Leslie, Bean, Kenneth Elwood, Padovani, Francois Antoine
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US05/423,630
• Time in Patent Office: 946 Days
• Field of Search: 357/30, 357/55
• US Class Current: 136/255
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/047 PV cell arrays including PV cells having multiple vertical junctions or multiple V-groove junctions formed in a semiconductor substrate
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/088 J-Fet, i.e. junction field effect transistor
• CPC Class Codes: Y10S 148/115 Orientation
• CPC Class Codes: Y10S 438/965 Shaped junction formation

Abstract

Disclosed is a method of fabricating a vertical multi-junction cell and the solar cell produced thereby, utilizing an orientation dependent etch to selectively provide parallel grooves in monocrystalline silicon body, followed by the introduction of doping impurities of the opposite conductivity type from the silicon body to provide PN junctions. In some instances the grooves are filled with silicon of the same conductivity type as the silicon body.

Claims

1. A semiconductor device in a monocrystalline semiconductor body of one conductivity type;

a. a plurality of spaced parallel semiconductor columns of one conductivity type, each having a thickness about 10 microns, extending out from said body; and

separated by grooves having a depth of about 100 microns;

b. a continuous semiconductor region of opposite conductivity type in said columns, adjacent the surfaces thereof and in said body between said columns to form a continuous PN junction; and

c. a pattern of metal contacts on the top surface of said columns and on the opposite surface of said body.

2. The device as defined in claim 1, including a high conductivity semiconductor region of said one conductivity type in said substrate adjacent the opposite surface thereof.

3. The device defined in claim 1, wherein said body and said column are silicon.

4. The device as defined in claim 3, wherein the top surfaces of said columns are sharply pointed to minimize reflection.

5. The device of claim 1 wherein said PN junction is passivated at the surface of the semiconductor.