Digital arithmetic synthesizer phase lock loop with direct doppler and frequency readout
First Claim
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1. The combination comprising:
- phase comparator means for producing a digital number representing the difference in phase between an input signal and a synthesized signal;
clock means for producing periodic clock pulses;
first accumulator means responsive to said clock pulses for accumulating the digital number from said phase comparator means to produce a variable digital number;
storage means for storing a fixed digital number;
adder means responsive to said variable and said fixed digital numbers for producing a digital frequency number;
second accumulator means responsive to said clock pulses for accumulating successive digital frequency numbers to produce a digital phase number; and
converter means responsive to said digital phase number for producing the synthesized signal.
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Abstract
Arithmetic frequency synthesizer, for use in a phase locked loop, having a partitioned frequency register to provide direct representation of doppler and repeatibility of frequency. Included are provisions for sweeping a range of signal frequencies of interest to acquire a lock on a desired signal within that range.
30 Citations
6 Claims
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1. The combination comprising:
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phase comparator means for producing a digital number representing the difference in phase between an input signal and a synthesized signal; clock means for producing periodic clock pulses; first accumulator means responsive to said clock pulses for accumulating the digital number from said phase comparator means to produce a variable digital number; storage means for storing a fixed digital number; adder means responsive to said variable and said fixed digital numbers for producing a digital frequency number; second accumulator means responsive to said clock pulses for accumulating successive digital frequency numbers to produce a digital phase number; and converter means responsive to said digital phase number for producing the synthesized signal. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification