Digital data transmission system

• US 3,974,403 A
• Filed: 11/11/1974
• Issued: 08/10/1976
• Est. Priority Date: 06/30/1972
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Georgopoulos, Christos J.
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US05/522,384
• Time in Patent Office: 638 Days
• Field of Search: 307/208, 307/246, 307/254, 307/263, 307/268, 307/270, 307/237
• US Class Current: 326/90
• CPC Class Codes: H03K 17/0826 in bipolar transistor switches
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults

Abstract

A driver circuit for a digital data transmission system is provided with a transistor current limiting network, the network being bypassed by a capacitor. The network is selectively supplied with a disabling signal via another transistor to disconnect the driver circuit from its power supply in the event of a short circuit condition.

Claims

1. In a digital system, the combination comprising:

a. a transmission line;

b. a plurality of input/output devices coupled to such transmission line, each one of such plurality of devices having an output transistor coupled to a voltage supply through a first transistor; and

,

c. means for inhibiting a flow of current from the voltage source, through the first transistor, to the output transistor, such inhibiting means including an electronic switch coupled to the base electrode of the first transistor of each one of the plurality of input/output devices.

2. In a driver circuit for supplying current from a voltage source to a load selectively in accordance with a binary control signal, such current passing to such load through a current limiting network, the improvement comprising:

a. a capacitor having a first electrode coupled to the current limiting network and a second electrode coupled to the load and the voltage source; and

b. switching means having;

An input terminal coupled to the first electrode of the capacitor and current limiting network;

an output terminal coupled to the load; and

a control terminal coupled to a source of the binary control signal, decoupling the capacitor, the current limiting network and the voltage source from the load to enable the capacitor to charge through the current limiting network from the voltage source, and, during a second state of the linear control signal, for coupling the capacitor, the voltage source and the current limiting network to the load to enable current to flow to such load initially from the discharge of the capacitor and thereafter from the source through the current limiting network; and

, wherein the current limiting network includes a drive transistor coupled between the first electrode of the capacitor and the voltage source;

the switching means includes an output transistor coupled between the load and the first electrode of the capacitor; and

, including additionally biasing means for enabling the capacitor to provide a path for discharging minority carriers stored within the output transistor during the first state, such biasing means including;

A resistor coupled between the voltage source and an input electrode of the drive transistor; and

a current limiting transistor, one electrode thereof being coupled to the input electrode of the drive transistor, and a third electrode thereof being connected to the base electrode of the drive transistor and wherein the biasing means includes an electronic switching means coupled to the base electrode of the drive transistor for providing a control voltage to the base electrode of the drive transistor selectively to turn such drive transistor "on" or "off" in accordance with such control voltage.