Capacitive voltage converter employing CMOS switches

• US 3,975,671 A
• Filed: 02/24/1975
• Issued: 08/17/1976
• Est. Priority Date: 02/24/1975
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stoll, Peter A.
• Primary Examiner(s): Goldberg, Gerald
• Application Number:
  US05/552,439
• Time in Patent Office: 540 Days
• Field of Search: 321/15, 307/109, 307/110, 357/42, 357/59
• US Class Current: 363/60
• CPC Class Codes: G04G 19/04 Capacitive voltage division or multiplication
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A CMOS circuit for approximately tripling battery voltage particularly adaptable for use with liquid crystal displays such as used in watches. P-wells of the CMOS circuit are coupled to active circuit nodes rather than to battery potentials. In the presently preferred embodiment a hybrid circuit with external capacitors is used to increase overall efficiency.

Claims

1. An MOS integrated circuit disposed on a substrate of a first conductivity type, for coupling a capacitance means to a source of potential such that said capacitance means may be charged from said source of potential, and for coupling said capacitance means to a connection means comprising:

a first well of a second conductivity type disposed on said substrate;

said well being coupled to said capacitance means;

a first transistor disposed in said first well, said first transistor including a pair of regions of said first conductivity type, one of said regions coupled to said source of potential and the other of said regions coupled to said capacitance means; and

,

a second transistor, said second transistor including a pair or regions of said first conductivity type, one of said regions coupled to said capacitance means and the other region coupled to said connection means;

whereby said capacitance means may be charged from said source of potential then coupled in series with said source of potential or other capacitance means to provide a higher output potential.

2. The circuit defined by claim 1 wherein said second transistor is disposed in a well of said second conductivity type.

3. The circuit defined by claim 2 wherein said first conductivity type is n-type.

4. A CMOS integrated circuit disposed on a substrate of a first conductivity type for charging a capacitor from a source of potential, and for coupling said capacitor in series with said source of potential to provide a higher potential than said source of potential, said source of potential including a first and second potential terminal and said capacitor including a first and second capacitor terminal, comprising:

a first transistor disposed on said substrate, said first transistor including a pair of regions of a second conductivity type, one of said regions coupled to said first potential terminals and the other of said regions coupled to said first capacitor terminal;

a first p-well, said first p-well coupled to said second potential terminal;

a second transistor disposed in said first p-well said second transistor including a pair of regions of said first conductivity type, one of said regions coupled to said first capacitor terminal and the other of said regions coupled to said second potential terminal;

a second p-well disposed in said substrate, said second p-well coupled to said second capacitor terminal;

a third transistor disposed in said second p-well, said third transistor including a pair of regions of said first conductivity type, one of said regions coupled to said second potential terminal and the other of said regions coupled to said second capacitor terminal;

a fourth transistor disposed on said substrate, said fourth transistor including a pair of regions of said first conductivity type, one of said regions coupled to said second capacitor terminal;

a fifth transistor disposed on said substrate, said fifth transistor including a pair of regions of said second conductivity type, one of said regions coupled to said first potential terminal and the other of said regions providing a common terminal with said other region of said fourth transistor;

whereby said capacitor may be charged from said source of potential and then coupled in series with said source of potential to provide a higher potential at said common terminal.

5. The circuit defined by claim 4 wherein said fourth transistor is disposed within a p-well.

6. The circuit defined by claim 5 wherein said p-well of said fourth transistor is coupled to said second capacitor terminal.

7. The circuit defined by claim 4 wherein said first conductivity type is n-type.