Phase sequence detector for three-phase AC power system

• US 3,976,919 A
• Filed: 06/04/1975
• Issued: 08/24/1976
• Est. Priority Date: 06/04/1975
• Status: Expired due to Term

• Current Assignee: Baker Hughes Incorporated (Baker Hughes Company)
• Original Assignee: BorgWarner Incorporated
• Inventors: Ellis-Anwyl, David R., Vandevier, Joseph E.
• Primary Examiner(s): Miller, J D
• Assistant Examiner(s): Salce, Patrick R.
• Application Number:
  US05/583,719
• Time in Patent Office: 447 Days
• Field of Search: 317/47, 317/27 R, 317/46, 317/13 R, 317/33 SC, 328/133, 328/155, 324/83 R, 324/83 D, 324/83 A, 324/86, 307/232, 307/127, 340/253 H, 340/253 Y, 318/683
• US Class Current: 361/96
• CPC Class Codes: G01R 29/18 Indicating phase sequence; Indicating synchronism
• CPC Class Codes: H02H 11/004 in case of incorrect phase sequence; with switching for obtaining correct phase sequence protection of motors against wrong direction of rotation H02H7/097
• CPC Class Codes: H02H 7/097 against wrong direction of rotation

Abstract

The phase sequence of the phase currents supplied by a three-phase AC power supply to a phase-sensitive load (such as a three-phase AC motor) is monitored by developing three phase-displaced, rectangular shaped logic signals, respectively representing the three phase currents, and applying these logic signals to respective ones of the J, C and K inputs of a J-K flip-flop. When the load is correctly connected to the power supply, the phase relationship of the three logic signals will be appropriate to trigger the flip-flop to its set operating state. Any other sequence actuates the flip-flop to its reset state which, in turn, disconnects the load from the power supply.

Claims

1. A phase sequence detector for monitoring the phase sequence of the three phase currents supplied by a three-phase AC power supply to a phase-sensitive three-phase load to determine if a predetermined desired phase sequence exists, thereby determining whether the power supply is correctly connected to the load, comprising:

a flip-flop having set and reset operating states and having first, second and third inputs for actuating said flip-flop to its two operating states, said flip-flop triggering to its set operating state in response to the application of an actuating signal to said second input at the same time that a certain signal condition is present on said first input and triggering to its reset state in response to the application of an actuating signal to said second input when a given signal condition is present on said third input;

means responsive to the three phase currents supplied to the three-phase load for providing first, second and third phase-displaced, control signals each of which is a function of and represents a respective one of the three phase currents;

means for applying said first, second and third control signals to said first, second and third inputs, respectively, said first and second control signals effecting actuation of said flip-flop to its set operating state when said predetermined desired phase sequence is present and said second and third control signals causing actuation of said flip-flop to its reset state if any other phase sequence exists;

and means responsive to and controlled by said flip-flop for providing an indication of the operating state of said flip-flop.

2. A digital logic phase sequence detector for monitoring the phase sequence of the three phase currents supplied by a three-phase AC power supply to a phase-sensitive, three-phase load to determine if a predetermined desired phase sequence exists, thereby determining whether the power supply is correctly connected to the load, comprising:

a flip-flop having set and reset operating states and having first, second and third inputs for actuating said flip-flop to its two operating states, said flip-flop triggering to its set operating state if a positive-going pulse transition is applied to said second input when said first input is established at a logic 1 signal level and actuating to its reset state if a positive-going pulse transition is applied to said second input when said third input is established at a logic 1 signal level,

means responsive to the three phase currents supplied to the three-phase load for producing first, second and third phase-displaced, generally rectangular shaped logic signals each of which alternates between logic 1 and logic 0 levels and each of which represents and is a function of a respective one of the three phase currents, the logic 1 pulse components of said first logic signal embracing the positive-going transitions of said second logic signal and the logic 1 pulse components of said second logic signal overlapping the positive-going transitions of said third logic signal when said predetermined desired phase sequence is present;

means for applying said first, second and third logic signals to said first, second and third inputs, respectively, to establish said flip-flop in its set operating state if said predetermined desired phase sequence exists and in its reset operating state if said predetermined desired phase sequence is absent;

and means controlled by said flip-flop for providing an indication of the operating state of said flip-flop.

3. A digital logic phase sequence detector according to claim 2 and including means controlled by said flip-flop for disconnecting the load from the AC power supply when said flip-flop is in its reset operating state.

4. A digital logic phase sequence detector according to claim 2 in which said flip-flop is a J-K flip-flop having J, C and K inputs respectively constituting said first, second and third inputs.

5. A digital logic phase sequence detector according to claim 2 in which said first, second and third logic signals are produced by three voltage comparators to which are applied, respectively, three sinusoidal signals each of which is developed from a respective one of the three phase currents.