Coupler for providing data transfer between host and remote data processing units

• US 3,976,979 A
• Filed: 01/02/1974
• Issued: 08/24/1976
• Est. Priority Date: 01/02/1974
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Austin, Joseph M., Parkinson, Kelvin L.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/430,110
• Time in Patent Office: 965 Days
• Field of Search: 340/172.5, 445/1
• US Class Current: 703/25
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A system for providing bidirectional data transfer between a host data processor and a remote data processor including coupler means responsive to the host processor for forcing the remote processor to provide such bidirectional data transfer even though the remote processor system software has failed and is unusable and/or even though the remote processor may be in a stopped state. Means are also provided for handling different word sizes which are normally processed in the respective processors, in order to properly interface such processors.

Claims

1. A system for providing bidirectional data transfer between a host processor and a remote processor, wherein said host processor is configured to process words of a first length and wherein said remote processor is configured to process words of a second length, said system including a coupler for interfacing said processors, said coupler comprising:

A. means for detecting any one of a plurality of data transfer commands from said host processor, said data transfer commands including read and write data transfer commands;

B. an input register coupled for receiving data from said host processor;

C. an output register coupled for receiving data from said remote processor;

D. first means for transferring data from said input register to said remote processor;

E. second means for transferring data from said output register to said host processor;

F. means for enabling said first and second means for transferring for the transfer of data from either said input or output registers to respectively said remote and host processors in response to either said write or read commands respectively;

G. status word register means comprising a plurality of bit locations, some of said locations for indicating whether a read or write data transfer command has been detected, said register means further including

1. an input counter, and

2. an output counter;

H. first means for changing the value of said input counter in response to a transfer of a subportion of a said word of said first length from said host processor to said input register;

I. second means for changing the value of said output counter in response to a transfer of a subportion of a said word of said second length from said output register to said host processor;

J. conversion means responsive to said input and output counter, including;

3. A system as in claim 1 wherein said first means for providing included in said conversion means comprises:

A. a plurality of logic gates;

B. means, responsive to said input counter, for enabling a plurality of said gates equal in number to the number of bits in said subportion of said words for transfer of a said subportion of a said word to said input register; and

C. means, responsive to said input counter, for enabling different said pluralities of said gates until all subportions of a said word are included in said input register.

4. A system as in claim 1 wherein said second means for providing included in said conversion means comprises:

A. a plurality of logic gates;

B. means, responsive to said output counter, for enabling a plurality of gates equal in number to the number of bits in said subportion of said words for transfer of a said subportion of a said word to said host processor; and

C. means, responsive to said output counter, for enabling different said pluralities of said gates until all subportions of a said word are transferred to said host processor.

5. A system as in claim 1 further comprising means, including an address register and a range register, for indicating the starting address in a memory included in said remote processor and the range of addresses starting from said starting address to or from which said data is to be transferred with said input or output registers.

6. A system as in claim 4 further comprising:

A. means for transferring the contents of said status word register means to said remote processor; and

B. means, responsive to the contents of said status word register means, for loading the contents of said address register and said range register.

7. A system as in claim 4 wherein said data transfer commands include a forced read command and a forced write command and further comprising means for enabling a forced transfer of data from either said input or output registers to respectively said remote and host processors in response to a predetermined condition, said means for enabling said forced transfer comprising:

A. means for generating a special interrupt signal in response to the detection of either a said forced read or forced write data transfer command;

B. means, responsive to said interrupt signal, for presetting said address register to an address of a predetermined location in said remote processor'"'"'s memory from which said remote processor may initiate a forced data transfer sequence;

C. means, responsive to said interrupt signal, for presetting said range register to an initial value indicative of at least one predetermined operation;

D. means for transferring said address of said predetermined location and said initial value to said remote processor;

E. means, responsive to said interrupt signal, for presetting said input register with an initial address of a predetermined group of locations in said remote processor'"'"'s memory, said group of locations including a plurality of commands for enabling said forced data transfer sequence;

F. means, responsive to the processing of said at least one predetermined operation, for providing said initial address to said remote processor; and

G. means, responsive to said plurality of commands, for enabling said data transfers even though the normal means for providing such data transfers in said remote processor is unuseable.

8. A system as in claim 6 wherein said means for forcing said transfer of data further comprises means, responsive to said interrupt signal, for disabling any further interrupt signals from being received by said remote processor.

2. first means for providing a conversion of a said word of said first length to a said word of said second length, andsecond means for providing a conversion of a said word of said second length to a said word of said first length;

and