Digital polynomial function generator

• US 3,978,326 A
• Filed: 12/18/1975
• Issued: 08/31/1976
• Est. Priority Date: 12/27/1974
• Status: Expired due to Term

• Current Assignee: Naonobu Shimomura
• Original Assignee: Naonobu Shimomura
• Inventors: Shimomura, Naonobu
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US05/641,950
• Time in Patent Office: 257 Days
• Field of Search: 235/152, 235/156, 235/197
• US Class Current: 708/446
• CPC Class Codes: G06F 2207/5523 Calculates a power, e.g. the square, of a number or a function, e.g. polynomials
• CPC Class Codes: G06F 7/552 Powers or roots , e.g. Pythagorean sums

Abstract

Apparatus for obtaining a numerical value of a polynomial function of a variable. The method of cascade accumulation is used in which memories M0, M1, M2, . . . , Mn are involved, and under one cycle of manipulation, the content of memory M1 is added to the content of M0, the content of M2 is added to the content of M1, and so on until the content of Mn is added to the content of Mn-1. By loading a digital value determined by the coefficients of the polynomial a₀, a₁, a₂, . . . , a_n in each of the memories as its initial value, and repeating x cycles of the above mentioned manipulations, the digital value of the function

w = a.sub.0 + a.sub.1 x + a.sub.2 x.sup.2 + . . . +  a.sub.n x.sup.n

is obtained in the memory M0.

A simplified electrical circuit for performing the above manipulation is disclosed, in one example of which only memories or a shift register and an adder are involved as key elements in the logic circuit to generate a polynomial function, and no complicated programming is needed.

Claims

1. Apparatus for obtaining a digital value of a function expressed by:

space="preserve" listing-type="equation">w = a.sub.0 + a.sub.1 x + a.sub.2 x.sup.2 + . . . + a.sub.n x.sup.n

where

w is the function the value of which is to be obtained,

a₀, a₁, a₂, . . . , a_n are constants,

x is the independent variable,

n is an integer and n≧

2,

comprising;

a shift register means composed of blocks B0, B1, B2, . . . , Bn having equal bit lengths of storage and arranged in the order of B0, B1, B2, . . . , Bn and having first and second output terminals and an input terminal, means for loading each block of said shift register means with respective specific numerical value determined by the constants a₀, a₁, a₂, . . . , a_n,

control means for supplying shift pulses to said shift register blocks to shift the contents of said blocks of said shift register means,

means for reading out serially the contents of said shift register means in response to said shift pulses in the order of B0, B1, B2, . . . , Bn from said first output terminal, and, simultaneously, in the order of B1, B2, . . . , Bn from said second output terminal of said shift register means,

a serial full adder means having two input terminals and one output terminal,

means for supplying said read out digits from said first output terminal of said shift register means to one of the input terminals of said full adder means,

means for supplying said read out digits from said second output terminal of said shift register means to the other of the input terminals of said full adder means,

means for supplying the digits from said output terminal of said full adder means to said input terminal of said shift register means to be rewritten therein,

said control means, for performing one cycle of cascade additions, supplying a number of shift pulses selected in number in accordance with the number of storage bits of said blocks of said shift register means to shift the bits through all blocks of said shift register, said one cycle of cascade additions being divided into n+1 equal time intervals during each of which the bits of each block are shifted to the next successive block in said shift register means,

means for interrupting the digits read out from said second output terminal of said shift register means to be supplied to the other input terminal of said full adder means during the last one of said time intervals, and

said control means performing a number of cycles of cascade additions corresponding to the value of the independent variable x, thereby to obtain the value of the function w in the block B0 of said shift register means.

2. Apparatus as claimed in claim 1, wherein said shift register means comprises a plurality of serial memory means connected in series, and said second output terminal of said shift register means comprises a series connection point of two successive said memory means.

3. Apparatus as claimed in claim 1, wherein said means for interrupting the digits read out from said second output terminal of said shift register means to be supplied to the other input terminal of said full adder means during the last one of said time intervals comprises a gate connected in series between said second output terminal of said shift register means and the other input terminal of said full adder means and having an inhibit terminal,

said control means supplying an inhibit signal to said inhibit terminal during said last one of said time intervals.

4. Apparatus as claimed in claim 1, wherein said full adder means includes a carry output terminal and a carry input terminal, and further includes an inhibit gate having an inhibit terminal, said inhibit gate being connected in series between said carry output terminal and carry input terminal, and

said control means applies an inhibit signal to said inhibit terminal between the last shift pulse of one of said time intervals and the first shift pulse of the succeeding time interval.

5. Apparatus as claimed in claim 1, wherein there is further included complementer means connected in series between said second output terminal of said shift register means and said other input terminal of said full adder means.