Multi-terminal controlled-inversion semiconductor devices

• US 3,979,613 A
• Filed: 06/18/1975
• Issued: 09/07/1976
• Est. Priority Date: 06/18/1975
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation (Unisys Corporation)
• Original Assignee: Sperry Rand Corporation (Unisys Corporation)
• Inventors: Kroger, Harry, Wegener, Horst A. R.
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US05/587,939
• Time in Patent Office: 447 Days
• Field of Search: 357/23, 357/52, 357/57, 307/304
• US Class Current: 327/530
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 2213/33 Material including silicon
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0895 Tunnel injectors
• CPC Class Codes: H03K 19/02 using specified components H03K19/0005 - H03K19/0021, H03K19/003 - H03K19/0175 take precedence
• CPC Class Codes: H03K 3/36 by the use, as active elements, of semiconductors, not otherwise provided for

Abstract

Multi-terminal controlled-inversion semiconductor devices are presented having current or voltage controllable switching characteristics provided through use of a non-linear resistive layer and by the control of the rate of injection of carriers with respect to their rate of removal by conduction through the non-linear layer.

Claims

1. Controlled inversion semiconductor circuit means comprising:

semiconductor body means having first and second spaced surface means,

non-linear resistive layer means affixed to said first surface means,

conductive layer means affixed to said non-linear resistive layer means opposite said semiconductor body means,

first electrical signal source means for applying a first control signal between said conductive layer means and said second surface means,

minority carrier generator means within said semiconductor body means for generating an inversion layer within said semiconductor body means at said non-linear resistive layer means when said first control voltage reaches a predetermined threshold value,

said non-linear resistive layer means tending to prevent formation of said inversion layer when said first control signal remains below said predetermined threshold value,

second electrical signal source means for applying a second control signal between said second surface means and ohmic contact means disposed on said semiconductor body means between said minority carrier generator means and said non-linear resistive layer means for further controlling the supply of minority carriers reaching said inversion layer, and

utilization means in series relation with said first electrical signal source means and said conductive layer means.

2. Apparatus as described in claim 1 wherein said ohmic contact means is disposed on said semiconductor body means between said minority carrier generator means and said first surface means.

3. Apparatus as described in claim 1 where said semiconductor body means comprises first and second semiconductor layer means of respective first and second semiconductor conductivity types for forming semiconductor junction minority carrier generator means therebetween.

4. Apparatus as described in claim 3 wherein said ohmic contact means is conductively coupled to said first semiconductor layer means.

5. Apparatus as described in claim 3 wherein said ohmic contact means is conductively coupled to said first semiconductor layer means between said semiconductor junction generator means and said first surface means.

6. Apparatus as described in claim 1 wherein said semiconductor body means comprises silicon.

7. Apparatus as described in claim 6 wherein said non-linear resistive layer means comprises a pyrolytically deposited nitride of silicon.

8. Apparatus as described in claim 1 wherein said minority carrier generator means provides means for generating a substantial inversion layer at said non-linear resistive layer means in a first state of resistivity thereof and substantially no inversion layer at said non-linear resistive layer means in a second state of resistivity thereof.

9. Apparatus as described in claim 1 wherein the signal amplitude of said second control signal is adjustable for selectively producing amplified current flow into said utilization means.

10. Apparatus as described in claim 1 wherein at least one of said first and second electrical signal source means is a source of pulsed electric signals.

11. Apparatus as described in claim 1 wherein said first and second electrical signal source means provide respective first and second pulsed electrical signals of first and second predetermined amplitudes whereby an amplitude current pulse flows into said utilization means upon substantial time overlap of a said first and a said second pulsed electrical signal.

12. Apparatus as described in claim 1 wherein said first and second electrical signal source means provide respective first and second control signals of first and second predetermined amplitudes whereby current flow is initiated into said utilization means upon substantial time overlap of said first and second control signals and continues even after said second control signal has ended only when said second control signal exceeds a predetermined amplitude.

13. Apparatus as described in claim 3 wherein said second electrical signal source means comprises variable impedance means coupled directly between said second surface means and ohmic contact means on said first semiconductor layer means for effecting synchronous application of said first and second control signals.

14. Apparatus as described in claim 3 wherein said second electrical signal source means comprises controlled inversion semiconductor means having first terminal means coupled to said second surface means, second terminal means coupled to ohmic contact means disposed on said first semiconductor layer means, and third terminal means coupled to third electrical signal source means.

15. Apparatus as described in claim 1 additionally including means for selectively illuminating said semiconductor body means in the presence of at least said first control signal current flow in said utilization means indicating the presence of illumination thereof above a predetermined light level.

16. Apparatus as described in claim 3 wherein one of said respective first and second conductivity types is type p while the other is type n.

17. Apparatus as described in claim 3 additionally including third semiconductor layer means interposed between said second semiconductor conductivity layer means and said non-linear resistive layer means.

18. Apparatus as described in claim 1 wherein said minority carrier generator means comprises metal barrier emitter means at said second surface.

19. Apparatus as described in claim 1 wherein said ohmic contact means is affixed to said semiconductor body means at said first surface means.

20. Apparatus as described in claim 19 wherein said ohmic contact means comprises ring-shaped annular metal electrode means.

21. Apparatus as described in claim 20 wherein said ohmic contact means is affixed on said first surface means in substantially concentric relation with respect to said non-linear resistive layer means.

22. Apparatus as described in claim 20 wherein said first semiconductor layer means is formed by epitaxial deposition upon said second semiconductor layer means.

23. Apparatus as described in claim 20 wherein said first semiconductor layer means is formed by diffusion of material within said semiconductor body means at said first surface means.

24. Apparatus as described in claim 3 wherein said first semiconductor layer means includes an annular region of third conductivity type at said first surface means, said ohmic contact means being disposed on said annular region of third conductivity type.