Maintenance monitor for telephone switching systems

• US 3,980,839 A
• Filed: 12/09/1974
• Issued: 09/14/1976
• Est. Priority Date: 12/09/1974
• Status: Expired due to Term

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: Lynch Communication Systems, Inc. (Nokia Corporation)
• Inventors: Hutcheson, Alan G.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US05/530,960
• Time in Patent Office: 645 Days
• Field of Search: 179/175.2 R, 179/175.2 C, 445/1
• US Class Current: 379/9
• CPC Class Codes: H04M 3/24 with provision for checking the normal operation

Abstract

A data processing system for monitoring a telephone switching system comprises a microprocessor controller, random access and read only memories, and data input and error output means. The data processing system analyzes the received data to determine if the switching system is operating correctly, and if it is not outputs coded information indicating the errors discovered and methods for switching system repair.

Claims

1. A data processing system for the monitoring and maintenance of an electronic switching system wherein the said processing system obtains data from said switching system indicating the present operating status of the switching system and the processing system detects and diagnoses operation errors based on the form of this said data and communicates these results to maintenance personnel, said processing system comprising:

a. processor means for analyzing and testing the switching system data to thereby detect and diagnose operation errors occuring in the said switching system;

b. system controller means for controlling the nature and sequence of the analysis done by said processor means;

c. memory means for the storage of data while it is manipulated by said processor means and system controller means and for the storage of ongoing switching system operation status;

d. data input means including

i. input data storage means and data input control means for the inputting and temporary storage of data supplied by said switching system independent of processor control, and

ii. means for coupling the input data from the input data storage means to the memory means when the processor means is ready to accept new data from analysis and testing; and

e. output means including

i. means for receiving said detected operation errors from the processor means and

ii. means for storing and outputting said detected operation errors.

2. The data processing system of claim 1 wherein the means for storing and outputting the said detected operation errors comprises means that operate independently of the processor means, memory means, or system controller means.

3. The data process system of claim 2 wherein the means for storing and outputting the detected operation errors further comprises:

a. output storage means for the retention of any detected errors until the retained errors are read out by maintenance personnel;

b. means arranged so that once the said output storage means are full to capacity with detected errors, no other errors are stored, so that the origin of a recurring switching system malfunction may be more easily discovered and repaired by maintenance personnel; and

c. display means for communicating to maintenance personnel the errors stored in the output storage means and operable by maintenance personnel independent of the processor means and system controller means, thereby allowing read-out of errors even though the processor means continues to analyze other data.

4. The data processing system of claim 3 wherein the output storage means further comprises of storage unit that does not require complex addressing but operates by shifting each error as it it stored in the said unit through to the output queue of the unit, so that if the said unit is initially empty, the first error stored automatically appears in the output port, for display, the next word stored is queued up against this word and so on, thereby requiring only a read and a write control line to operate the said unit.

5. The data processing system of claim 1 wherein the data input means further comprises input data converter means for insuring that received data is in the proper data block format for data analysis, wherein a data block comprises a plurality of words of one or more informational bits each.

6. The data processing system of claim 5 wherein the input data storage means comprises means for temporarily storing, to await data analysis, data in the form of a plurality of data blocks reflecting switching system operation, and comprises means for indicating that the said data input storage means are full and cannot accept any new data blocks.

7. The data processing system of claim 6 wherein the data input control means comprises:

a. means for controlling the input data converter means such that the correct number of data words comprising the data block are inputted to the data input storage means;

b. means for disallowing new data to be read into the data input storage means, if the data input storage means are full;

c. means for disallowing new data to be read into the data input storage means while data is being read out of the same said storage means; and

d. means for coupling, after receiving a request for a new block of data by the processor means for analysis, the next data block from the data input storage means to the said memory means independently of the processor means and system control means, wherein the number of words in a data block is kept track of by counter means in the data input control means to insure that only the plurality of words in one block is coupled through, no more and no less, and wherein the center means further comprises means for addressing the proper area of the said memory means to insure that the data block is properly coupled to the memory means.

8. The data processing system of claim 7 wherein the switching system data blocks, if received from two separate subsystems of the switching system, can be inputted into separate data input storage means and controlled by separate data input control means, for later comparison of the data after analysis by the processor means and for protection against the possible loss of data, if this data is essentially the same from either source, for any given switching system operation that is monitored.

9. The data processing system of claim 8 wherein the input data storage means further comprises a storage unit which does not require complex addressing but operates by shifting each data word as it is stored in the said unit through to the output queue of the said unit, so that if the said unit is initially empty the first word stored automatically appears at the output port, the next word stored is queued up behind this word, and so on, thereby requiring only a read and a write control line to operate the said unit.

10. The data processing system of claim 1 wherein the memory means comprises a random access memory.

11. The data processing system of claim 1 wherein the processor means comprises microprocessor means and state decoder means.

12. The data processing system of claim 11 wherein the microprocessor means comprises a miniaturized electronic assembly including an input/output register, an arithmetic logic unit, an accumulator register, a plurality of temporary storage registers, a program counter, a clock generator, an instruction and decode and control unit, and means for coupling signals from one register or unit to another, for the implementation of various instructions as decoded by the instruction decode and control unit, and comprising a plurality of data lines connected to the input/output register to couple the microprocessor means to external systems and a plurality of microprocessor control lines to further couple the microprocessor means operationally to external systems.

13. The data processing system of claim 12 wherein the state decoder means comprises means for taking the said microprocessor control lines and generating a plurality of system control lines for use in processing system operation.

14. The data processing system of claim 13 wherein the system controller means comprises a control cycle including a list of control instructions for the manipulation of the microprocessor means and for control over the state of the said system control lines outputted by the microprocessor means.

15. The data processing system of claim 14 wherein the control cycle is embodied in non-erasable read only memory means comprising a plurality of memory locations containing the said list of control instructions for processing system manipulation.

16. The data processing system of claim 15 wherein the read only memory means further comprises a list of constants that contain information as to the proper operation of the switching system for the facilitation of switching system data analysis and error detection by the system controller means and microprocessor means.

17. A data processing system for the monitoring and maintenance of an electronic switching system including data input means, processor means, system controller means, memory means and error output means, wherein the said processing system formats data from the said switching system into data blocks having a plurality of words of one or more informational bits each, and then stores the data to await data analysis, said data input means comprising:

a. input data proper means for insuring that received data is in the priper data block format for data analysis;

b. input data storage means comprising means for temporarily storing data in the form of a plurality of data blocks reflecting switching system operation to await data analysis, and comprising means for indicating that the said data input storage means are full and cannot accept new data blocks; and

c. data input control means comprising;

1. means for controlling the input data converter means such that the correct number of data words comprising the data block are inputted to the data input storage means;

19. The data processing system of claim 17 wherein the counter means further comprises means for addressing the proper area of the said memory means to insure that the data block is properly coupled to the memory means.

18. means for disallowing new data to be read in if the data input storage means are full;

3. means for disallowing new data to be read into the data input storage means while data is being read out of the same storage means; and

4. means after receiving a request for a new block of data by the processor means for analysis, for coupling the next data block from the data input storage means to the said memory means independent of the microprocessor means and system control means, wherein the number of words in the data block is kept track of by counter means in the data input control means to insure that only the plurality of words in one data block is coupled through, no more and no less.

20. The data processing system of claim 18 wherein the input data storage means further comprises a storage unit which does not require complex addressing but operates by shifting each data word as it is stored in the said unit through to the output queue of the said unit, so that if the said unit is initially empty the first word stored automatically appears at the output port, the next word stored is queued up behind this word, and so on, thereby requiring only a read and a write control line to operate the said unit.

21. A data processing system for the monitoring and maintenance of an electronic switching system including a processor unit under the control of system controller means that analyzes data received from the said switching system and outputs detected errors in the operation of said switching system via output means, said output means comprising:

a. output storage means for the retention of any detected errors until these errors are read out by maintenance personnel;

b. means whereby once the said output storage means are full to capacity with detected errors, no other errors are stored, so that the origin of a recurring switching system malfunction may be more easily discovered and repaired by maintenance personnel; and

c. display means for the communication to maintenance personnel of the said errors stored in the output storage means, operable by maintenance personnel independent of the processor unit and system controller means thereby allowing read out of errors even though the processor unit continues to analyze other data.

22. The data processing system of 20 wherein the output storage means further comprises a storage unit that does not require complex addressing but operates by shifting each error as it is stored in the said unit through to the output queue of the unit, so that if the said unit is initially empty, the first error stored automatically appears in the output port, for display, the next word stored is queued up against this word and so on, thereby requiring only a read and a write control line to operate the said unit.

23. A data processing system for the monitoring and maintenance of an electronic telephone switching system wherein said processing system obtains data from said switching system, said processing system existing and operating apart from said switching system, and wherein the processing system detects and diagnoses operation errors based on the form of said data and communicates these results to maintenance personnel, said processing system comprising:

a. microprocessor means comprising a microprocessor and state decoder means for analyzing and testing the telephone switching system data to thereby detect and diagnose operation errors occuring in the said switching system;

b. system controller means for controlling the nature and sequence of the analysis done by said microprocessor means;

c. memory means for storage of telephone switching system status and temporary storage of current switching system data being analyzed;

d. data input means for inputting and temporarily storing data supplied by said switching system, including means for coupling said input data to the memory means when said data is requested by said microprocessor means; and

e. error output means for the communication of detected telephone switching system operation errors to maintenance personnel.

25. A method as in claim 23 further including the steps of:

a. determining if a switching system power-up has occured, and if so, resetting all switching system path status memory locations in said memory means;

b. detecting if a processing system restart has occurred or if a system clear switch has been actuated, and if so, resetting said path status memory locations in said processing system that do not contain valid data as determined by the state of a history bit in each said status location; and

c. performing other special tests, as required, to initialize the processing system.

26. The method of claim 23 wherein step (e) further includes the steps of:

a. storing in an output queue means each of said errors prior to actuating said indicating means; and

b. waiting for manual actuation of switch means prior to outputting said errors from said queue means to said indicating means, said manual actuation enabling said indicating means thereby to display errors in the sequence in which they were detected by said processing system.

27. A method as in claim 23 further including the steps of:

a. electronically detecting the operating state of said switching system to determine whether an operating signal path has been ended;

b. electronically determining whether the path attempted or ended by said switching system originated at the remote end or the central office end of the switching system; and

c. electronically performing error tests on the data generated by steps (a) and (b) and outputting errors, if found, in the same manner as for errors found in said attempted path data.

24. In a data processing system including input storage means, memory means, controller means, and error indicator means, a method of detecting errors in an external electronic switching system comprising the steps of:

a. detecting electronically the operating state of said switching system for determining thereby whether said switching system has attempted a new operating signal path;

b. if an operating signal path has been attempted, storing data representing the specific path attempted in a queue in said input storage means behind other previously-stored path attempt data;

c. transferring said specific path attempted data to said memory means when the controller means is ready to test the next path for errors and said path data is at the front of the queue;

d. electronically testing said specific path attempted data with information representing the former status of that path, said path status also stored in said memory means, to determine whether or not the path attempted is in fact created and whether the path is the proper path chosen;

e. if an error is found by said tests, actuating said error indicating means, so that said error is displayed thereby;

f. if no error is found in the new path, updating said path status in said memory means to reflect this new path; and

g. repeating of steps (a) through (f).