Traffic signal loop monitoring system

• US 3,980,867 A
• Filed: 12/19/1974
• Issued: 09/14/1976
• Est. Priority Date: 12/19/1974
• Status: Expired due to Term

• Current Assignee: Display Technologies, Inc. (Rhode Island)
• Original Assignee: Indicator Controls Corporation
• Inventors: Potter, Thomas R.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Vandenburg, John P.
• Application Number:
  US05/534,634
• Time in Patent Office: 635 Days
• Field of Search: 235/92 T, 235/92 TF, 235/92 CA, 235/92 PE, 235/92 TC, 235/92 CT, 235/92 DN, 235/92 MT, 340/248 R, 340/248 D, 340/248 E, 340/38 R
• US Class Current: 377/52
• CPC Class Codes: G01R 23/15 Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)
• CPC Class Codes: G08G 1/042 using inductive or magnetic detectors
• CPC Class Codes: H03K 21/38 Starting, stopping or resetting the counter counters with a base other than a power of two H03K23/48, H03K23/66

Abstract

A monitoring system is provided for use in conjunction with a wire loop which is embedded in a roadway, and which senses the presence of vehicles in the roadway to control a traffic signal. The monitoring system senses the output of the loop oscillator which is included in the traffic control circuitry and which generates a loop signal and whose frequency-determining circuit includes the wire loop to indicate immediately any failure in the loop circuit. If for any reason the loop oscillator fails to operate, that fact will be sensed immediately by the monitoring system of the invention, and such a failure will be equated to a failure in the embedded loop, or in the lead-in circuit which connects the loop to the loop oscillator. A digital embodiment of the monitoring system of the invention includes a reference oscillator which generates a reference signal whose frequency is lower than the frequency of the loop signal, and it also includes a two-count binary counter which is clocked by the reference signal, and which is cleared by the loop signal so that the counter cannot exceed a count of one, so long as the loop oscillator is functioning. However, should the loop oscillator fail, indicating a failure condition in the loop, the counter will then proceed to the count of two, and that count will set a flip-flop to activate an appropriate indicator. The flip-flop will remain set and the indicator activated, until reset by appropriate manual means. An analog embodiment of the monitoring system of the invention is also provided.

Claims

1. A monitoring system for detecting a failure condition in an electrical network, said network including an inductive loop, a loop oscillator and a lead-in circuit connecting the inductive loop to the oscillator to cause the oscillator to generate a loop signal having a frequency (f_L) determined by the inductance of the loop and lead-in circuit, said monitoring system including:

control circuit means connected to said loop oscillator and including a reference source and comparator means coupled to the reference source and to the output of the loop oscillator and responsive to the loop signal for producing an output signal having a first value in the presence of said loop signal and a second value in th absence of said loop signal.

2. The monitoring system of claim 1, in which said control circuit means comprises a reference oscillator for generating a reference signal having a frequency (f_R) which is less than the frequency (f_L) of the loop signal;

a binary counter;

first circuit means connecting the reference oscillator to the binary counter to cause the reference signal to clock the counter and tend to cause the counter to proceed from one count to the next for each successive cycle of the reference signal;

second circuit means connecting the loop oscillator to the counter to cause the loop signal to clear the counter for each successive cycle of the loop signal; and

output circuit means connected to the counter for normally producing said output signal at said first value, and for detecting when the counter proceeds beyond a predetermined count to produce said output signal at said second value.

3. The monitoring system defined in claim 2, in which the counter is a two-count counter;

and in which said output circuit means detects when the counter proceeds beyond the one count.

4. The monitoring system defined in claim 3, in which said counter includes a first and second flip-flop interconnected with one another.

5. The monitoring system defined in claim 4, in which said output circuit means includes a third flip-flop which is connected to the second flip-flop and which is set when the second flip-flop is set.

6. The monitoring system defined in claim 5, in which said third flip-flop, when set, remains set until reset by a manual resetting means.

7. The monitoring system defined in claim 1, and which includes indicator means connected to said control circuit means to be activated when said output signal is at said second value.

8. The monitoring system defined in claim 6, and which includes indicator means connected to said third flip-flop to be activated when said third flip-flop is set.

9. The monitoring system defined in claim 1, in which said control circuit means comprises a rectifier circuit coupled to the output of said loop oscillator to produce a direct current output voltage having a value related to the peak amplitude of said loop signal;

and signal comparator means for producing an output whenever the direct current output voltage falls below a predetermined reference voltage level.

10. The monitoring system defined in claim 9, and which includes a memory element coupled to the comparator to be set by the output of said comparator for producing said output signal at said second value.

11. The monitoring system defined in claim 9, and which includes indicator means connected to said memory element to be activated when said output signal is at said second value.

12. The monitoring system defined in claim 10, in which said memory element, when set, remains set until reset by a manual re-setting means.