Continuously monitoring ratiometer

• US 3,981,586 A
• Filed: 05/19/1975
• Issued: 09/21/1976
• Est. Priority Date: 05/19/1975
• Status: Expired due to Term

• Current Assignee: Perkinelmer Incorporated
• Original Assignee: Perkinelmer Incorporated
• Inventors: Scott, Larkin B.
• Primary Examiner(s): Corbin, John K.
• Assistant Examiner(s): Evans, F. L.
• Application Number:
  US05/578,500
• Time in Patent Office: 491 Days
• Field of Search: 324/140 R, 324/140 D, 356/88, 356/93, 356/94, 356/95, 356/96, 356/97, 356/179, 356/195, 356/204, 356/205, 356/206, 356/211, 356/212, 328/161
• US Class Current: 356/323
• CPC Class Codes: G01J 1/18 using comparison with a reference electric value
• CPC Class Codes: G06G 7/161 with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form pulse modulators H03K7/00

Abstract

An analytically significant ratio between timevarying magnitudes of signals is periodically monitored in recurring cycles which are each synchronized with a frequency generator. During every monitoring cycle, each signal relating to the numerator and denominator of the ratio, is integrated separately for a fixed number of generator cycles. Thereafter in each monitoring cycle, the output from the integrator of the denominator signal is applied at the input to the integrator of the numerator signal and the time taken by the latter to integrate back to its starting level is measured in proportion to the ratio of the signals. Either digital or analog time measurements may be utilized and the number of generator cycles over which the ratio is determined may include transition periods between each stage of integration.

Claims

1. Apparatus for continuously monitoring a ratio between two time-varying signals, comprising:

a first integrator for the signal relating to the denominator of the ratio;

a second integrator for the signal relating to the numerator of the ratio;

chopper means for applying each of the signals to said corresponding integrator;

sample and hold means for storing the output of said first integrator;

said sample and hold means having the output thereof connected to the input of said second integrator;

timer means for measuring the elapsed interval between when output from said sample and hold means is applied to said second integrator and when output from said second integrator transgresses through a reference level;

reset means for returning said timer means and each said integrator to reference levels;

a frequency generator; and

logic means for controlling said chopper means, the output from said sample and hold means, and said reset means in synchronized intervals with the cycles of said frequency generator, said chopper means being controlled to apply the signals to said integrators for at least one frequency cycle, the output from said sample and hold means being controlled for connecting to said second integrator only after integration of the numerator signal has been completed thereby, and said reset means being controlled to establish the reference levels only after the elapsed interval in proportion to the ratio of the signals has been measured by said timer means.

2. The apparatus of claim 1 wherein said frequency generator is an a.c. power line.

3. The apparatus of claim 1 wherein said chopper means and said reset means both include field effect transistor switches within said logic means.

4. The apparatus of claim 1 wherein said sample and hold means includes an operational amplifier having the output thereof shunted to the inverting input thereof and having the noninverting input thereof grounded through a capacitor.

5. The apparatus of claim 1 wherein said first and second integrators each include an operational amplifier having a capacitor connected between the output and the inverting input thereof and having the noninverting input thereof grounded.

6. The apparatus of claim 1 wherein said timer means includes a level detecting comparator, a ramp generator and a d.c. voltage reference, said comparator having the input thereof connected to the output from said second integrator and the output thereof connected to control a gate within said logic means to apply said reference voltage at the input of said ramp generator throughout the elapsed interval measurement.

7. The apparatus of claim 1 wherein said chopper means applies the signals to said integrators during alternate intervals and wherein a gate in said logic means controls input to said sample and hold means, the output from said first integrator being stored in said sample and hold means prior to completion of the interval for said second integrator.

8. The apparatus of claim 1 wherein said chopper means receives the signals from a photoelectric detector within a spectrophotometer having a beam switch therein, said beam switch being synchronized with said frequency generator to alternately direct beams of radiant energy to said photoelectric detector from both sample and reference paths said photoelectric detector generating output signals I and I₀ in proportion to the intensity of said sample and reference beams respectively, said I₀ and I signals being applied to said first and second integrators respectively by said chopper means with the elapsed interval measured by said timer means being proportional to the ratio of I/I₀.

9. The apparatus of claim 8 wherein said beam switch includes a synchronous motor and applies each of the sample and reference beams to said photoelectric detector for a duration of two frequency cycles.

10. In a spectrophotometer having a beam switch which alternately directs beams of radiant energy to a photoelectric detector from sample and reference paths therein, said photoelectric detector generating output signals I and I₀ in proportion to the intensity of the sample and reference beams respectively, the improvement comprising:

a first integrator including a first operational amplifier with a capacitor connected between the output and the inverting input thereof and with the noninverting input thereof grounded;

a second integrator including a second operational amplifier with a capacitor connected between the output and the inverting input thereof and with the noninverting input thereof grounded;

sample and hold means including a third operational amplifier with the output thereof shunted to the inverting input thereof and with the noninverting input thereof grounded through a capacitor;

a comparator including a fourth operational amplifier with the inverting input thereof connected to the output of said second operational amplifier and with the noninverting input thereof grounded;

a ramp generator including a fifth operational amplifier with a capacitor connected between the output and the inverting input thereof and with the noninverting input thereof grounded; and

logic means for synchronizing individual switches with a.c. power to the spectrophotometer, and with output from said comparator;

said first operational amplifier having the inverting input thereof connected to the output from said photoelectric detector through a first of said switches;

said second operational amplifier having the inverting input thereof connected to the output from said photoelectric detector through a second of said switches;

said third operational amplifier having the noninverting input thereof connected to the output of said first operational amplifier through a third of said switches and having the output therefrom connected to the inverting input of said second operational amplifier through a fourth of said switches;

said fifth operational amplifier having the inverting input thereof connected to a d.c. reference voltage through a fifth of said switches;

said first, second and fifth operational amplifiers each having the output thereof shunted to the inverting input thereof through a sixth, seventh and eighth of said switches respectively;

said logic means programming said switches to periodically derive the ratio of I/I₀ over identical monitoring periods of eight power cycles;

said first switch being programmed to close for the first and second power cycles;

said second switch being programmed to close for the fourth and fifth power cycles;

said third switch being programmed to close for the fourth power cycle;

said fourth switch being programmed to close for the sixth, seventh, eighth and first power cycles;

said fifth switch being programmed to close during the sixth, seventh, eighth and first power cycles for as long as output from said second operational amplifier exceeds the comparator threshold level on the noninverting input of said fourth operational amplifier;

said sixth switch being programmed to close for the sixth power cycle; and

said seventh and eighth switches being programmed to close for the second power cycle.