Voltage maintenance apparatus

• US 3,982,141 A
• Filed: 10/07/1974
• Issued: 09/21/1976
• Est. Priority Date: 10/07/1974
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Copeland, John Alexander III
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US05/512,849
• Time in Patent Office: 715 Days
• Field of Search: 307/238, 307/221 C, 307/296, 307/247 A
• US Class Current: 327/198
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: H02J 9/06 with automatic change-over , e.g. UPS systems

Abstract

A capacitor in parallel with a CMOS memory is used, in the event of a power outage, to apply a sufficient temporary voltage to the memory to maintain the stored data. Data storage retention time is maximized by a resistor, connected between the capacitor and the memory, having a resistance R approximately given by

R = 0.4 (V.sub.i - V.sub.f)/I.sub.f                        (1)

where V_i is the initial voltage on the capacitor, V_f is the minimum voltage for maintaining the data and I_f is the capacitor discharge current at voltage V_f.

Claims

1. In combination:

a semiconductor memory having a resistance-voltage characteristic which is similar to MOS memories;

said memory being adapted to be connected in parallel with a d-c power supply for applying to the memory a voltage V_i ;

said memory being capable of storing electrical data provided the applied voltage is a minimum value V_f ;

means for temporarily maintaining an applied voltage between V_f and V_i in the event of accidental disconnection of the power supply comprising a capacitor in parallel with the memory and the power supply;

3. The combination of claim 1 wherein:

the memory is a CMOS memory.

5. The combination of claim 3 wherein:

the resistor has a resistance R substantially given by

space="preserve" listing-type="equation">R = 0.4 (V.sub.ci - V.sub.f)/I.sub.f

where I_f is the capacitor discharge current at voltage V_f, and V_ci is the initial voltage across the capacitor.

2. and means for increasing the time during which the applied voltage can be temporarily maintained above V_f comprising a resistor which is other than any internal resistance of the capacitor, connected between the capacitor and the memory, the resistor having a resistance R substantially defined by the Equation R "= 0.4 (V_ci - V_f)/I_f where I_f is the capacitor discharge current at voltage V_f and V_ci is the initial voltage across the capacitor.

4. In combination:

a CMOS memory;

said memory being adapted to be connected in parallel with a power supply for applying to the memory a voltage V_i ;

said memory being capable of storing electrical data provided the applied voltage is a minimum value V_f ;

means for temporarily maintaining an applied voltage between V_f and V_i in the event of accidental disconnection of the power supply comprising a capacitor in parallel with the memory and the power supply;

and means for increasing the time during which the applied voltage can be temporarily maintained above V_f comprising a resistor, which is other than any inherent internal resistance of the capacitor, connected between the capacitor and the memory.