Processor for use between keyboard telephone set and television set

• US 3,984,638 A
• Filed: 01/21/1975
• Issued: 10/05/1976
• Est. Priority Date: 01/21/1975
• Status: Expired due to Term

• Current Assignee: Christian P. Carrouge
• Original Assignee: Christian P. Carrouge
• Inventors: Carrouge, Christian P.
• Primary Examiner(s): Claffy, Kathleen H.
• Assistant Examiner(s): Popek, Joseph A.
• Application Number:
  US05/542,801
• Time in Patent Office: 623 Days
• Field of Search: 179/2 R, 179/2 A, 179/2 DP, 179/2 TV, 340/324 A, 340/324 AD, 178/6.8
• US Class Current: 379/93.18
• CPC Class Codes: H04M 11/085 using a television receiver, e.g. viewdata system

Abstract

Processor for use between an earpiece of a keyboard telephone set serving to interrogate a computer by means of multi-frequency code interrogation signals and to receive from said computer digital serial answer words beginning with a start signal and frequency modulating an answer carrier, and a television set for displaying alpha-numeric characters corresponding to these digital answer words. The conventional telephone sets include means for inhibiting the answer signals from being applied to the earpiece when a key of the keyboard is depressed. Also when a key of the telephone set is depressed on overvoltage is produced across the earpiece terminals which would give rise to false start signals if no precaution was taken. Accordingly, the processor comprises a frequency demodulator for receiving the frequency modulated signals corresponding to values zero and one of the bits of the answer words, a receive register controlled by the start signals and means for allowing the frequency demodulator to generate a zero output signal when the frequency of the frequency modulated carrier has the value corresponding to a selected binary value, one or zero, of the bits of the answer words so that, when a key of the keyboard of the telephone set is depressed and the answer frequency modulated carrier is then inhibited, the output signal from the demodulator is the same as when a modulation frequency corresponding to said selected value is received.

Claims

1. In a processor for use between an earpiece of a keyboard telephone set serving to interrogate a computer by means of multifrequency code interrogation signals and to receive from said computer digital serial answer words beginning with a start signal and frequency modulating an answer word carrier, and a television set for displaying alpha-numeric characters corresponding to the digital answer words, said telephone set including means for inhibiting the answer frequency modulated carrier from being applied to said earpiece when a key of said keyboard is depressed for multifrequency code interrogation signal transmission, the improvement consisting of:

a frequency demodulator for receiving the frequency modulated signals corresponding to values zero and one of the bits of the answer words;

a receive register controlled by said start signals for storing the digital answer words;

a read only memory of alpha-numeric characters addressed by said digital words;

a spatial addressing device addressing by lines and columns the alpha-numeric characters on the screen of the television set; and

adjustment means controlled by said frequency demodulator to generate a zero output signal when the input frequency of the frequency modulated carrier has a value corresponding to one of the binary values of the bits of the answer words, so that, when a key of the keyboard of the telephone set is depressed and the answer frequency modulated carrier is then inhibited, the output signal from the demodulator is the same as when a modulation frequency corresponding to said one of the binary values is received;

said adjustment means including frequency control means to limit the frequencies of the multi-frequency code range between approximately 697 and 1477Hz and the carriers corresponding to the values 0 and 1 of the bits of the answer words ranging approximately between 1650 and 1850 Hz, said frequency modulator being thereby adjusted at 1650 Hz by said adjustment means, so that, when the demodulator receives a signal at 1650 Hz and when it does not receive any such signal, it produces in both cases a zero output signal.

2. A processor as claimed in claim 1, in which, in order to take into account false starts due to the overvoltage across the terminals of the earpiece of the telephone set when a key of the keyboard is depressed, the receive register which stores the digital answer words controlled by the start signals comprises gating means for inhibiting the received words formed by bits which all have the binary value corresponding to the frequency of the frequency modulated carrier at which the frequency demodulator is allowed to generate a zero output signal.

3. A processor as claimed in claim 1, in which the alpha-numeric characters in the read only memory are characters in the form of matrices of points arranged in 7 lines and 5 columns.