Push-pull amplifier circuitry

• US 3,986,134 A
• Filed: 08/15/1975
• Issued: 10/12/1976
• Est. Priority Date: 08/23/1974
• Status: Expired due to Term

• Current Assignee: Nippon Yusen Kabushiki Kaisha
• Original Assignee: Nippon Yusen Kabushiki Kaisha
• Inventors: Yokoyama, Kenji
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US05/605,172
• Time in Patent Office: 424 Days
• Field of Search: 330/13, 330/15, 330/19, 330/30 D, 330/28, 330/35, 330/18
• US Class Current: 330/269
• CPC Class Codes: H03F 3/3044 Junction FET SEPP output stages H03F3/3008 takes precedence

Abstract

A push-pull amplifier circuitry comprising: a first and a second FET (abbreviation of field effect transistor which will be used hereinafter) of an n-channel type, a third FET of a p-channel type with its gate and source connected to the gate of said first FET and to the source of said second FET respectively, a fourth FET of a p-channel type having a gate and a source connected to the gate of said second FET and to the source of said first FET, a positive voltage supply connected to the drain of said first FET and via a resistor to the drain of said second FET and, a negative voltage supply connected to the drain of said third FET and via another resistor to the drain of said fourth FET. This circuitry is suitable for use as an input stage or an interstage amplifier circuit such as a pre-driver of a multistage direct-coupled push-pull amplifier.

Claims

1. A push-pull amplifier circuitry comprising:

a first and a second field effect transistor (FET) of an n-channel type both having a gate electrode, a drain electrode and a source electrode;

a third FET of a p-channel type having a gate electrode and a source electrode connected to the gate electrode of said first FET and to the source electrode of said second FET, respectively, and having a drain electrode;

a fourth FET of a p-channel type having a gate electrode and a source electrode connected to the gate electrode of said second FET and to the source electrode of said first FET, respectively, and having a drain electrode;

a positive voltage supply connected to the drain electrode of said first FET and via a first resistor to the drain electrode of said second FET;

a negative voltage supply connected to the drain electrode of said third FET and via a second resistor to the drain electrode of said fourth FET;

a first input terminal of said push-pull amplifier circuitry connected to the coupled gate electrodes of said first and said third FET'"'"'s;

a second input terminal of said push-pull amplifier circuitry connected to the coupled gate electrodes of said second and said fourth FET'"'"'s;

a first output terminal of said push-pull amplifier circuitry connected to the drain electrode of said second FET and,

a second output terminal of said push-pull amplifier circuitry connected to the drain electrode of said fourth FET.

2. A push-pull amplifier circuitry according to claim 1, further comprising:

a third resistor connected in series between the source electrodes of said first and said fourth FET'"'"'s and,

a fourth resistor connected in series between the source electrodes of said second and said third FET'"'"'s.

3. A push-pull amplifier circuitry according to claim 1, in which:

said first and said second resistors both have a same resistance and,

said positive and said negative voltage supplies both generate a same absolute value of the output voltage.

4. A push-pull amplifier circuitry according to claim 2, in which:

said first and said second resistors both have a same resistance,

said third and said fourth resistors both have a same resistance and,

said positive and said negative voltage supplies both generate a same absolute value of the output voltage.

5. A push-pull amplifier circuitry according to claim 1 employed in the pre-driver stage of a four-stage direct-coupled push-pull amplifier, in which the amplifier circuitry further comprises:

An input stage including a fifth and a sixth FET of an n-channel type both having source electrodes connected respectively via a constant current circuit to said negative voltage supply, and having drain electrodes connected respectively via resistors to said positive voltage supply and direct-coupled with said first and second input terminals of the pre-driver stage, and both having gate electrodes;

an input terminal of said direct-coupled amplifier connected to the gate electrode of said fifth FET;

a driver stage including a seventh and an eighth FET respectively being a p-channel and an n-channel type and both having their drain electrodes connected to each other via a variable resistor, and having source electrodes connected respectively via a resistor to said positive and negative voltage supplies, and having their gate electrodes direct-coupled respectively to said first and said second output terminals of the pre-driver stage;

a power stage including a ninth FET of p-channel type and a tenth FET of an n-channel type both having their gate electrodes of said seventh and said eighth FET'"'"'s in the drive stage, and having drain electrodes connected respectively to another negative and another positive voltage supplies, and having their source electrodes connected respectively to an output terminal of the direct-coupled amplifier;

a load connected between said output terminal and a ground; and

a resistor network composed of a plurality of resistors connected between said output terminal and the gate electrode of said sixth FET.

6. A push-pull amplifier circuitry according to claim 5, in which said constant current circuit comprises an FET of an n-channel type having its gate electrode and source electrode connected to said negative voltage supply and, via a resistor, to said negative voltage supply, and its drain electrode connected to a sliding tap of a rheostat whose opposite ends are connected across the sources of said fifth and sixth FET'"'"'s.

7. A push-pull amplifier circuitry according to claim 1 employed in the input stage of a three-stage direct-coupled push-pull amplifier, in which the amplifier circuitry further comprises:

an input terminal of the direct-coupled amplifier which is connected to said second input terminal of the input stage;

a driver stage including an FET of a p-channel type and an FET of an n-channel type both having their drain electrodes connected to each other via a variable resistor, and having their source electrodes connected via a resistor to said positive and said negative voltage supplies respectively, and having their gate electrodes direct-coupled to said first and said second output terminals, respectively, of the input stage;

a power stage including an FET of a p-channel type and an FET of an n-channel type both having their gate electrodes direct-coupled to the drain electrodes, respectively, of said FET'"'"'s in the driver stage, and having their drain electrodes connected to another negative voltage supply and to another positive voltage supply, respectively, and having their source electrodes connected together to an output terminal of the direct-coupled amplifier,

a load connected between said output terminal and a ground, and

a resistor network composed of a plurality of resistors connected between said output terminal and the first input terminal in the input stage.