Storage system comprising a main store and a buffer store

• US 3,986,171 A
• Filed: 11/20/1974
• Issued: 10/12/1976
• Est. Priority Date: 12/21/1973
• Status: Expired due to Term

• Current Assignee: Digital Equipment Corporation (HP Inc.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Spoelder, Gerrit Adriaan
• Primary Examiner(s): Nusbaum, Mark E.
• Application Number:
  US05/525,649
• Time in Patent Office: 692 Days
• Field of Search: 340/172.5, 445/1
• US Class Current: 711/3
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]

Abstract

A storage configuration comprising a main store, a buffer store having a smaller storage capacity, and an associated address store, comprising an address generator in which successive addresses can be generated for identification of the words of the buffer store. Also provided are means whereby the successive addresses can be taken up in the address locations of the address store, with the result that the buffer store can be addressed as a store having successive addresses by way of the address store.

Claims

1. A data processing system including a processor and a storage configuration including a first store and a relatively faster second store, wherein data is organized in each of said stores in at least one data class and wherein each data class is composed of at least one word block having a predetermined number of words of data, each word having a plurality of word portions, the number of words in said second store being less than the number of words in said first store, comprising

means for supplying from said processor a predetermined word block address a predetermined word block for addressing individual word blocks within said first and second store;

means for storing said predetermined word block address;

address store address store means for storing addresses of word blocks stored in said second store;

comparison means for comparing said stored predetermined word blocks address with said addresses stored in said third means, and for producing a selecting signal if said stored predetermined word block address does not correspond with said addresses stored in said third means;

selection means responsive to said selecting signal for effecting a transfer of said predetermined word block from said first store to said second store;

transfer means responsive to said selecting signal for effecting a transfer of said predetermined word block address from said second means to said address store means; and

activating means for modifying the mode of addressing said second store;

address generator means responsive to said activating means, for generating successive addresses of word blocks in said second store and loading these addresses in said address store means for addressing said second store.

2. A system as defined in claim 1, wherein said address generator means further comprises an inverter for inverting said successive addresses generated so that said second store is addressed through said address store means by means of successive inverted addresses.

3. A data processing system including a processor and a storage configuration including a first store and a relatively faster second store, wherein data is organized in each of said stores in at least one data class and wherein each data class is composed of at least one word block group the number of word groups in said first and second store being equal, said word blocks each having a predetermined number of word blocks of data, said second store having fewer word blocks per group than said first store, comprising

an address store divided into a number of groups of address blocks equal to the number of groups of word blocks of said first store, the number of address blocks thereof for each of said groups being equal to the number of word blocks for each of said groups of said second store;

data selection means for selecting data for processing by said processor from said first store and said second store, comprising

group selection means and block selection means

comparison means connected to said address store for comparing the address of a word block of a word requested from a selected group selected by said group selection means with the address blocks stored in the address store in said selected group selected by said group selection means of word blocks present in said second store;

means for generating a selection signal for selecting the relevant word block in the selected group in the first store when said comparison means indicates non-corresponce;

means for generating a selection signal for selecting the relevant word block in the selected group in said second store when said comparison means indicates correspondence;

activating means for modifying the mode of addressing said second store;

means for generating successive addresses of data in said second store, responsive to said activating means, including a first address portion of each of said successive addresses for group selection and a second address portion of each of said successive addresses for selection of a predetermined word block of the group of said second store selected by first address portion and for transferring these addresses to said address store; and

said address store further comprising means for receiving the second address portion in said address blocks of said selected group as determined by said group selection means, for addressing said second store as a store having successive addresses.