Discrete Fourier transform via cross correlation charge transfer device

• US 3,987,292 A
• Filed: 06/02/1975
• Issued: 10/19/1976
• Est. Priority Date: 06/02/1975
• Status: Expired due to Term

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Means, Robert W.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/583,086
• Time in Patent Office: 505 Days
• Field of Search: 235/181, 235/193, 235/150.53, 235/152, 235/156, 307/221 C, 307/221 D, 357/24
• US Class Current: 708/4
• CPC Class Codes: G06J 1/005 for correlation; for convolution; for Z or Fourier Transform

Abstract

A circuit for generating a discrete Fourier transform in real time employs a digital and analog shift register, each cell of which is tapped to feed an analog switch. The outputs of the individual analog switches are fed to a summing bus where the switched analog signals combine to form the desired Fourier transform.

Claims

1. A signal processor to produce a Fourier transform of an analog signal having a plurality of data points comprising:

digital shift register means having a plurality of cells for recirculating a digital clocking signal;

a charge coupled device configured as an analog shift register means having a plurality of cells for receipt and circulation of an analog signal at a predetermined rate different from that of said digital shift register;

a plurality of analog switch circuits each connected to a cell of said digital shift register by means of a direct, unweighted tap and connected to a corresponding cell of said analog shift register by means of a weighted tap which is weighted according to the expression;

space="preserve" listing-type="equation">e.sup.i.sup.π

k.spsp.2/2N

where;

k = integers between 0 and (N-1), and

N = one-half the number of cells in said analog shift registers plus one; and

summing means connected to each of said plurality of analog switches for receipt of the switched outputs therefrom, whereby a composite Fourier transform of the analog signal received by said analog shift register means is obtained.

2. A signal generator according to claim 1 in which the signal transfer rate of the said analog shift register is one half that of said digital shift register.

3. A signal processor circuit according to claim 1 in which said digital shift register means, said analog shift register means and said plurality of analog switch circuits have a number of cells and individual circuits, respectively, equal to one less than twice the number of the data points of the desired Fourier transform.

4. A signal processor according to claim 3 in which the signal transfer rate of the aforesaid analog shift register is one half that of the aforesaid digital shift register.