Programmable general purpose analog filter

• US 3,987,293 A
• Filed: 08/04/1975
• Issued: 10/19/1976
• Est. Priority Date: 08/04/1975
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation (Unisys Corporation)
• Original Assignee: Sperry Rand Corporation (Unisys Corporation)
• Inventors: Crooke, Arthur W., Wegener, Horst A. R.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/601,897
• Time in Patent Office: 442 Days
• Field of Search: 235/193, 235/194, 307/221 D, 307/221 C, 307/221 R, 307/229, 328/167, 328/160, 333/70 T, 333/18, 333/28, 325/42
• US Class Current: 708/819
• CPC Class Codes: H03H 15/02 using analogue shift registers
• CPC Class Codes: H03H 2015/026 Matched filters in charge domain

Abstract

A programmable transversal filter employig two charge transfer delay lines one for sampling a reference function, the samples providing the weighting factors for the transversal filter; the other for sampling an input signal to the filter. Each sample of the input signal is then multiplied by the appropriate weighting factor obtained from the sampling of the reference signal and all products are summed to obtain a sample of the filter output.

Claims

1. A programmable general purpose filter comprising:

input signal sampler means, having an input terminal and a plurality of output terminals, each output terminal providing a sample of an input signal applied to said input terminal;

reference signal sampler means having an input terminal and a plurality of output terminals, the number of output terminals being equal to the number of output terminals contained in said input signal sampler, each output terminal corresponding to one of said output terminals of said input signal sampler and providing a sample of a reference signal applied to said input terminal;

a plurality of multipliers equal in number to the number of output terminals of said input signal sampler, each multiplier being coupled to an output terminal of said input signal sampler and to said corresponding output terminal of said reference signal sampler, each of said multipliers having an output terminal at which a signal representative of the multiplication of said input signal sample by said reference signal sample is provided; and

summation means coupled to each of said output terminals of said plurality of multipliers for providing a signal representative of the sum of the products of said input signal samples by said reference signal samples, said sum being the sampled output response to said sampled input signal of a programmed filter defined by said sampled reference signal.

2. A programmable general purpose filter is accordance with claim 1 further including:

buffer register means having a plurality of input terminals and a plurality of output terminals, the number of input and output terminals being equal to the number of output terminals contained in said input signal sampler, each output terminal corresponding to one of said input terminals and each of said input terminals coupled to one of said output terminals of said reference signal sampler, and said corresponding output terminals coupled to said one of said multipliers corresponding to said output of said reference signal sampler, thereby storing samples of said reference signal at said one of said reference signal sampler terminals and providing said samples to said one of said multipliers.

3. A programmable general purpose filter in accordance with claim 2 further including:

memory means for storing digital reference signals;

converter means, coupled to said memory means and to said input terminal of said reference signal sampler, for converting digital signals to analog signals, whereby digital reference signals stored in said memory means are coupled to said reference signal sampler as analog reference signals.

4. A programmable general purpose filter in accordance with claim 1 further including:

second input signal sampler means having an input terminal and a plurality of output terminals, each output terminal corresponding to one of said output terminals of said input signal sampler and coupled to said one of said multipliers to which said corresponding output terminal of said input signal sampler is coupled, each output terminal providing a sample of a signal applied to said input terminal;

first inverter means, having an input terminal coupled to said input terminal of said input signal sampler means and an output terminal coupled to said input terminal of said second input signal sampler means, for providing a signal at said output terminal that is the negative of the signal applied at said input terminal, whereby the negative of said sample at one of said output terminals of said input signal sampler couples to said output terminal of said second input signal sampler corresponding thereto;

second reference signal sampler means having an input terminal and a plurality of output terminals, each output terminal corresponding to one of said output terminals of said reference signal sampler and coupled to said one of said multipliers to which said corresponding output terminals of said reference signal sampler is coupled, each output terminal providing a sample of a signal applied to said input terminal;

second inverter means, having an input terminal coupled to said input terminal of said reference signal sampler means and an output terminal coupled to said input terminal of said second reference signal sampler means, for providing a signal at said output terminal that is the negative of the signal applied at said input terminal, whereby the negative of said sample at one of said output terminals of said reference signal sampler couples to said output terminal of said second reference signal sampler corresponding thereto.

5. A programmable general purpose filter in accordance with claim 4 wherein each of said multipliers contains a first output terminal and a second output terminal and further including:

first summing means coupled to each of said first output terminals of said multipliers having an output terminal for providing a signal representative of the sum of the signals at each of said first output terminals of said multipliers;

second summing means coupled to each of said second output terminals of said multipliers having an output terminal for providing a signal representative of the sum of the signals at each of said second output terminals of said multipliers;

means, having a first input terminal, a second input terminal and an output terminal, coupled to said output terminal of said first summing means at said first input terminal and to said second summing means at said second input terminal, for providing a signal at said output terminal that is representative of the difference of said signals at said output terminals of said first and second summing means, whereby said signal at said output terminal is representative of the sum of the products of said samples of said input signal and said samples of said reference signal.

6. A digitally programmable general purpose filter in accordance with claim 4 further including:

memory means, having an input terminal and an output terminal, for storing digital reference signals;

converter means, having an input terminal and an output terminal, said input terminal coupled to said output terminal of said memory means and said output terminal coupled to said input terminals of said second inverter and said reference signal sampler, for converting digital signals to analog signals, whereby digital reference signals stored in said memory are coupled to said reference signal samplers as analog reference signals.

7. A programmable general purpose filter in accordance with claim 6 further including:

first buffer register means, having a plurality of input terminals and a plurality of output terminals, each of said input terminals coupled to one of said output terminals of said reference signal sampler and each of said output terminals coupled to one of said multipliers, whereby a sample of said reference signal at said one of said reference signal sampler output terminals is coupled to said one of said multipliers;

second buffer register means, having a plurality of input terminals and a plurality of output terminals, one of said input terminals coupled to one of said output terminals of said second reference signal sampler and one of said output terminals coupled to one of said multipliers, whereby a sample of said negative of said reference signal at said one of said second reference signal sampler output terminals is coupled to said one of said multipliers.

8. A signal multiplier comprising

first electronically controlled current means, having an input terminal, an output terminal, and a control terminal;

second electronically controlled current means, having an input terminal, an output terminal, and a control terminal, said control terminal coupled to said control terminal of said first electronically controlled current means;

third electronically controlled current means, having an input terminal, an output terminal, and a control terminal, said input terminal coupled to said input terminal of said first electronically controlled current means;

fourth electronically controlled current means, having an input terminal, an output terminal, and a control terminal, said input terminal coupled to said input terminal of said second electronically controlled current means and said control terminal coupled to said control terminal of said third electronically controlled current means;

difference amplifier means, having a first input terminal, a second input terminal, and an output terminal, the operation of which provides a signal at said output terminal representative of the difference between the signals at said first and second input terminals;

said first input terminal coupled to said output terminals of said first and fourth electronically controlled current means so that the sum of the currents at said output terminals of said second and fourth electronically controlled current means is coupled to said first input terminal,

said second input terminal coupled to said output terminals of said second and third electronically controlled current means so that the sum of the currents at said output terminals of said second and fourth electronically controlled current means is coupled to said input terminal,

whereby a signal representative of the product of a first signal with a predetermined polarity and a second signal with a predetermined polarity appears at said output terminal when said first signal with said predetermined polarity is applied to said first input terminal of said first and third electronically controlled current means, said first signal with polarity opposite to said predetermined polarity appears at said input terminal of said second and fourth electronically controlled current means, said second signal with said predetermined polarity appears at said control terminals of said first and second electronically controlled current means and said second signal with polarity opposite to said predetermined polarity appears at said control terminals of said third and fourth electronically controlled current means.

9. A signal multiplier in accordance with claim 8 wherein each of said electronically controlled current means is a MOSFET.