Control circuit

• US 3,995,208 A
• Filed: 04/25/1975
• Issued: 11/30/1976
• Est. Priority Date: 04/25/1975
• Status: Expired due to Term

• Current Assignee: Robert L. Parr
• Original Assignee: Robert L. Parr
• Inventors: Parr, Robert L.
• Primary Examiner(s): Dobeck, B.
• Application Number:
  US05/571,813
• Time in Patent Office: 585 Days
• Field of Search: 318/611, 318/612, 318/599, 318/341, 318/375, 318/379, 318/282
• US Class Current: 318/612
• CPC Class Codes: G05D 3/1472 with potentiometer
• CPC Class Codes: H02P 7/04 by means of a H-bridge circuit

Abstract

A control system for a d.c. motor, in which a cyclical d.c. drive signal is applied to the motor power input terminals as the system approaches balance. In each cycle, during at least part of the time interval between drive signal application to the motor terminals, a very low impedance (virtually a short circuit) is applied to the motor terminals. These braking pulses provide progressive braking as the motor approaches its balance point, limiting overshoot and ensuring a return without hunting from an overshoot condition to the balance point. As the system nears its deadband range, each braking pulse exceeds in duration the electrical time constant of the motor and constitutes a substantial portion of its associated cycle.

Claims

1. In a control system for a d.c. motor, said motor having a predetermined electrical time constant and having power input terminals, said control system having a balanced condition and first and second unbalanced conditions one on each side of said balanced condition, the improvement comprising:

a. means controllable for generating for application to said power input terminals a first drive signal of first polarity and a second drive signal of opposite polarity, said first drive signal tending to drive said motor from said first unbalanced condition toward said balanced condition and said second drive signal tending to drive said motor from said second unbalanced condition toward said balanced condition,

3. The invention according to claim 1 wherein the duration of each braking interval is greater than 50 percent of the duration of its associated cycle as said motor nears said balanced condition.

4. The invention according to claim 1 wherein said ratio is small when said motor is far from said balanced condition and becomes progressively larger when said motor nears said balanced condition, each braking interval being greater than 50 percent of the duration of each cycle as said motor nears said balanced condition.

5. The invention according to claim 3 wherein each braking interval is of duration greater than five times the time constant of said motor when said motor nears said balanced condition.

6. The invention according to claim 3 wherein each braking interval is of duration greater than ten times the time constant of said motor when said motor nears said balanced condition.

7. The invention according to claim 1 wherein said control system includes means controllable for producing a control signal indicative of the desired condition of said motor, means responsive to the condition of said motor for producing an error signal indicative of the actual condition of said motor, said motor being in balanced condition and said error signal having a predetermined value when the actual condition of said motor corresponds to the desired condition of said motor, said means (c) including means establishing a deadband range of said error signal about said predetermined value, in which variation of said error signal does not alter signals applied to said input terminals.

8. The invention according to claim 6 wherein said ratio is small when said motor is far from said balanced condition and each braking interval is at least as long as said time constant and occupies a substantial portion of its associated cycle when said error signal has a value which differs from said predetermined value by between 50 and 150 percent of the value of said deadband range.

9. The invention according to claim 6 wherein each braking interval occupies at least 50 percent of its associated cycle and is of duration greater than five times said time constant when said error signal differs from said predetermined value by between 50 and 150 percent of the value of said deadband range.

10. The invention according to claim 8 wherein said means (c) includes means for applying to said power input terminals, when said motor is in said balanced condition, a balanced signal comprising, cyclically and sequentially, said first drive signal, said second drive signal, and said low impedance, the application times of said first and second drive signals in said balanced signal being substantially equal and each application time of said low impedance being substantially longer than the application time of said first and second drive signals.

11. The invention according to claim 9 wherein said means (c) includes means for reducing said application times of said second drive signal and of said low impedance when said motor is in said first unbalanced condition and for reducing said application times of said first drive signal and of said low impedance when said motor is in said second unbalanced condition, whereby to produce a resultant drive signal for driving said motor from an unbalanced condition to said balanced condition.

12. The invention according to claim 9 wherein said means (c) includes means for progressively reducing the application times first of one of said drive signals, then of said low impedance when the condition of said motor changes from balanced to out of balance, and for progressively increasing the application times first of said low impedance and then of the reduced drive signal as said motor is restored to said balanced condition.

13. The invention according to claim 9 wherein, when said motor is in said balanced condition, each application time of said low impedance is at least 10 milliseconds.

14. The invention according to claim 12 wherein, when said motor is in said balanced condition, each application time of a said drive signal is of the order of 3 milliseconds and each application time of said low impedance is of the order of 17 milliseconds.

2. b. means controllable for applying a low impedance to said power input terminals,

c. means for sensing the condition of said motor and for controlling said means (a) and (b) for applying to said power input terminals,

i. when said motor is in said balanced condition, said low impedance for at least a substantial portion of the time when said motor is in said balanced condition,

ii. when said motor nears said balanced condition from said first unbalanced condition, a first composite signal comprising cyclically and sequentially said first drive signal and said low impedance,

iii. when said motor nears said balanced condition from said second unbalanced condition, a second composite signal comprising cyclically and sequentially said second drive signal and said low impedance,

d. each application of said low impedance to said power input terminals constituting a braking interval and the duration of each braking interval being at least as great as said time constant as said motor nears said balanced condition from either of said unbalanced conditions and when said motor is in said balanced condition,

e. said means (c) including means for controlling the ratio of the duration of each braking interval to the duration of its associated cycle so that such ratio increases as said motor nears said balanced condition from either unbalanced condition, and so that the duration of each braking interval is a substantial portion of its associated cycle as said motor nears said balanced condition, whereby to brake said motor progressively as it nears said balanced condition.