Seismic-acoustic detection device

• US 3,995,223 A
• Filed: 08/08/1972
• Issued: 11/30/1976
• Est. Priority Date: 02/19/1970
• Status: Expired due to Term

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Cotilla, Edward J., Picard, Salvatore R., Gimber, George A., Starry, Robert F.
• Primary Examiner(s): Hubler, Malcolm F.
• Application Number:
  US05/279,591
• Time in Patent Office: 1,575 Days
• Field of Search: 307/231, 307/232, 307/233, 307/225, 307/208, 340/258, 340/261, 340/258 R, 340/258 B, 181/.5 NP, 181/122, 328/109, 328/110
• US Class Current: 327/25
• CPC Class Codes: G01V 1/001 Acoustic presence detection
• CPC Class Codes: G08B 13/1663 using seismic sensing means

Abstract

A detection system for indicating the presence of motorized equipment in aesignated area having an acoustic sensor, a seismic sensor and an acoustic signal transmitter. The seismic sensor output, processed to discriminate against vibrations of short duration, is fed, along with the acoustic sensor output, to an "ANDing" circuit which gates the acoustic transmitter. The acoustic sensor output is passed to the transmitter only during coincidence of seismic and acoustic detection.

Claims

1. A detection logic system for providing a logic signal when a predetermined number of pulses in an input signal are received during a preselected first time interval beginning with the first pulse, comprising:

input gate means adapted to receive the input signal for producing an inverted replica signal thereof;

first timing means connected to receive the replica signal for providing a reset signal at the end of the first interval;

counter means coupled to receive the replica and reset signals for producing a first gating signal upon receiving one less than the predetermined number of replica signal pulses, said counter means resetting upon receiving the reset signal;

second timing means operatively connected to receive the replica signal for providing a second gating signal during a preselected second time interval shorter than the first interval; and

output gate means connected to receive the replica and gating signals for providing the logic signal upon coincidence of the received signals.

2. A detection logic system according to claim 1 wherein:

said output gate means includes a first AND gate connected to receive the first and second gating signals for providing a third gating signal to said input gate means for inhibiting the replica signal upon coincidence of the received signals, and a second AND gate connected to receive the replica signal and first gating signal for providing the logic signal upon coincidence of the received signals.

3. A detection logic system according to claim 2 further comprising:

third timing means connected to receive the logic signal for providing an inhibit signal to said first timing means for a preselected third time interval longer than the first interval.

4. A detection logic system according to claim 3 wherein:

said counter means includes first flip-flop means coupled to receive said replica signal for producing a signal corresponding to the counting of a second said pulse, and second flip-flop means coupled to receive said first flip-flop signal for producing a signal corresponding to a fourth said pulse, said flip-flop signals forming thereby the first gating signal to said first and second AND gates.

5. A detection logic system according to claim 1 wherein:

said output gate means includes a first AND gate receiving the replica and second gating signals for providing a third gating signal upon coincidence of the received signals, and a second AND gate receiving the first and third gating signals for providing the logic signal upon coincidence of the received signals.

6. A detection logic system according to claim 5 further comprising:

third timing means connected to receive the logic signal for providing an inhibit signal to said first timing means for a preselected third time interval longer than the first interval.

7. A detector logic system according to claim 6, wherein:

said counter means includes first flip-flop means coupled to receive said replica signal for producing a signal corresponding to the counting of a second said pulse, and second flip-flop means coupled to receive said first flip-flop signal for producing a signal corresponding to a fourth said pulse, said flip-flop signals forming thereby the first gating signal to said first and second AND gates.