Video generator circuit for a dynamic digital television display
First Claim
1. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, wherein the improvement comprises:
- an ordered refresh buffer connected to receive said data and adapted to sort said data signals into groups ordered by extremal scan line position for the pattern represented;
an intermediate buffer having a first input connected to the output of said ordered refresh buffer for storing said ordered data signals once during each display field before the display of the pattern represented and outputting said ordered data signals in synchronism with the line scan of the display;
a graphical pattern generator connected to the output of said intermediate buffer for decoding said ordered data signals outputted from said intermediate buffer and generating on a first output line components of the pattern represented which lie along the display line to be scanned;
a partial raster assembly storage connected to said first output line from said graphical pattern generator to store the components of the pattern represented which lie along the display line to be scanned;
said graphical pattern generator modifiying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said pattern represented with the next display line to be scanned, and outputting said modified data signal over a second output line to a second input line for storage in said intermediate buffer;
said graphical pattern generator omitting the output of a modified data signal on said second output line when no components of said pattern will intersect succeeding display lines to be scanned in said field.
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Accused Products
Abstract
A video generator is disclosed for use in a digital television display system, for converting randomly occurring data signals representing graphical patterns into a time-sequential video signal for use with a sequentially line scanned display device. The circuit is comprised of a threaded buffer connected to receive the data signals and adapted to sort the data signals into groups ordered by extremal scan line positions for the pattern represented. An intermediate buffer has a first input connected to the output of the threaded refresh buffer for storing the ordered data signals once during each display field before the display of the pattern represented and outputting the ordered data signals in synchronism with the line scans of the display. A graphical pattern generator is connected to the output of the intermediate buffer for decoding the ordered data signals outputted therefrom and generating on a first output line components of the pattern represented which lie along the display line to be scanned. A partial raster assembly storage is connected to the first output line from the graphical pattern generator, to store the components of the pattern represented which lie along the display line to be scanned. The graphical pattern generator modifies the decoded ordered data signals to identify the horizontal coordinate for the intersection of the pattern represented with the next display line to be scanned, and outputs the modified data signal over a second output line to a second input line for storage in the intermediate buffer. The graphical pattern generator omits the output of a modified data signal on the second output line when no components of the pattern will intersect succeeding display lines to be scanned in the field.
68 Citations
20 Claims
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1. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, wherein the improvement comprises:
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an ordered refresh buffer connected to receive said data and adapted to sort said data signals into groups ordered by extremal scan line position for the pattern represented; an intermediate buffer having a first input connected to the output of said ordered refresh buffer for storing said ordered data signals once during each display field before the display of the pattern represented and outputting said ordered data signals in synchronism with the line scan of the display; a graphical pattern generator connected to the output of said intermediate buffer for decoding said ordered data signals outputted from said intermediate buffer and generating on a first output line components of the pattern represented which lie along the display line to be scanned; a partial raster assembly storage connected to said first output line from said graphical pattern generator to store the components of the pattern represented which lie along the display line to be scanned; said graphical pattern generator modifiying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said pattern represented with the next display line to be scanned, and outputting said modified data signal over a second output line to a second input line for storage in said intermediate buffer; said graphical pattern generator omitting the output of a modified data signal on said second output line when no components of said pattern will intersect succeeding display lines to be scanned in said field. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A video generator circuit for converting randomly occurring data signals received from a host processor, representing graphical patterns into a time sequential video signal for use with a sequentially line scanned display device, wherein the improvement comprises:
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a threaded buffer connected to receive said data and adapted to sort said data signals into groups ordered by extremal scan line positions for the pattern represented; an intermediate buffer having a first input connected to the output of said threaded refresh buffer for storing said ordered data signals once during each display field before the display of the pattern represented and outputting said ordered data signals in synchronism with the line scan of the display; a graphical pattern generator connected to the output of said intermediate buffer for decoding said ordered data signals outputted from said intermediate buffer and generating on a first output line components of the pattern represented which lie along the display line to be scanned; a partial raster assembly storage connected to said first output line from said graphical pattern generator to store the components of the pattern represented which lie along the display line to be scanned; said graphical pattern generator modifiying said decoded ordered data signals to identify the horizontal coordinate for the intersection of said pattern represented with the next display line to be scanned, and outputting said modified data signal over a second output line to a second input line for storage in said intermediate buffer; said graphical pattern generator omitting the output of a modified data signal on said second output line when no components of said pattern will intersect succeeding display lines to be scanned in said field.
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Specification