High speed divide-by-two circuit

• US 3,997,796 A
• Filed: 05/14/1975
• Issued: 12/14/1976
• Est. Priority Date: 05/14/1975
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Sanders, David E., Chambers, Ramon P., Gordy, Robert S.
• Primary Examiner(s): Zazworsky, John
• Assistant Examiner(s): Rasco, Marcus S.
• Application Number:
  US05/577,373
• Time in Patent Office: 580 Days
• Field of Search: 328/25, 328/30, 328/39, 328/136, 307/220, 307/225 R, 307/271, 331/113 R
• US Class Current: 327/118
• CPC Class Codes: H03K 3/2823 using two active transistor of the same conductivity type H03K3/2821 takes precedence

Abstract

A high speed divide-by-two circuit operable in the 400 to 500 MHz frequency range comprising a pair of transistors having their emitters connected in common to an input circuit and their bases and collectors cross-coupled by a pair of capacitors. The collectors of the transistors are also coupled together by a single inductor.

Claims

1. A high speed divide-by-two circuit comprising:

a pair of transistors, each having collector, emitter and base electrodes;

an input circuit means coupled in common to the emitter electrodes of each of said transistors;

a pair of capacitors connecting the respective collector electrode of each transistor to the base electrode of the other transistor;

a coil connected directly between the collector electrodes of said transistors;

resistance means for connecting each of said collectors to a potential source;

biasing means connected to the bases of said transistors for biasing said transistors; and

an output terminal coupled to the collector electrode of one of said transistors.

2. The high speed divide-by-two circuit according to claim 1 wherein said input circuit means is a current amplifier comprised of:

a transistor having a collector, emitter and base electrode,

said collector electrode connected to the emitter electrodes of said pair of transistors, said base electrode coupled to an input, and said emitter electrode connected to a common reference potential.

3. The high speed divide-by-two circuit according to claim 1 and further comprising:

means for temperature compensating said biasing means.