Digital demodulator for differentially encoded phase-shift-keyed data

• US 3,997,847 A
• Filed: 10/29/1975
• Issued: 12/14/1976
• Est. Priority Date: 10/29/1975
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Tong, Shih Yung
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US05/626,659
• Time in Patent Office: 412 Days
• Field of Search: 329/104, 329/105, 329/110, 329/126, 325/349, 178/66 A
• US Class Current: 329/306
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

A demodulator for differentially coherent phase-shift keyed data signals correlates samples taken in consecutive baud intervals. Depending on the results of at least two such correlations or lack thereof, counts are registered in unidirectional counters supplied with thresholds related to preassigned counts per baud interval. Bistable circuits respond to the attainment, or failure of attainment, of the threshold-count levels during each baud interval, after which the counters are reset to a reference level. The states of the bistable circuits directly represent binary data without further logic operations in the four-phase case particularly.

Claims

1. Apparatus for demodulating a received data signaling wave encoding data elements by phase differences between successive signaling intervals comprising:

means for hard limiting said received wave to display polarity and zero crossings thereof only;

shift register means having a plurality of stages for serially storing periodic samples of the output of said hard-limiting means extending over more than a signaling interval;

means for comparing the instant sample of the received wave at the input of said shift register means with samples from the present and succeeding signaling interval stored therein,

said comparing means generating complementary outputs corresponding to matches and mismatches respectively between compared samples;

counting means responsive to outputs of said comparing means representing mismatches between pairs of compared samples and having preassigned threshold counts;

bistable circuit means responsive to the attainment or not of threshold count levels by said counting means in each signaling interval, the output state of said bistable circuit means corresponding to decoded digital data; and

means for resetting said counting means to a reference state at the beginning of each signaling interval.

2. Apparatus in accordance with claim 1 in which the encoding carrier phase differences are 90m electrical degrees, m being equal to 0, 1, 2 and 3;

and the phase separation between the input sample to said shift register means and the previous samples compared is one baud interval plus and minus π

/4 radians of the received wave.

3. Apparatus in accordance with claim 1 in which said comparing means comprise exclusive-OR gates having a first output state when input signals are alike and a second complementary output state when input signals are mutually complementary.

4. Apparatus in accordance with claim 1 in which said counting means count in one direction only in response to one binary input state and are resettable to a reference condition in response to another binary input.

5. Apparatus in accordance with claim 1 in which the number of periodic samples taken for each signaling interval is n, and the threshold count level for each of said counting means is not less than n/2.

6. Apparatus in accordance with claim 1 in which the number of periodic samples taken for each signaling interval is 256 and the threshold count level for each of said counting means is not less than 128.

7. A demodulator for differentially phase encoded digital data comprising storage means for a plurality of samples of received digital data encoded on n phases of a carrier wave of a given frequency,

first and second exclusive-OR means for correlating the input to said storage means with previous inputs separated by one baud interval plus and minus π

/n radians of said carrier wave to provide first and second bivalued correlation signals,

first and second resettable counter means responsive to said first and second correlation signals respectively and having preassigned threshold output count levels,

first and second bistable circuit means, and

means for gating the count-up state of said first and second counting means respectively to said first and second bistable circuit means at baud intervals to indicate whether or not the preassigned thresholds of said counter means have been crossed and for thereafter resetting said counter means to a reference condition, the resultant states of said bistable means representing decoded digital data.

8. The demodulator defined in claim 7 in which

digital data are encoded on four discrete phases of said carrier wave separated by 90 electrical degrees,

said storage means is a multistage shift register storing samples separated by at least one baud interval plus and minus 45 electrical degrees,

said first exclusive-OR gate compares a signal sample entering said storage means with another signal sample received one baud interval and 45 electrical degrees previously, and

said second exclusive-OR gate compares a signal sample entering said storage means with another signal sample received one baud interval less 45 electrical degrees previously.

9. The demodulator defined in claim 7 in which each discrete carrier phase difference between succeeding baud intervals encodes two binary digits and the output states of said bistable circuit means corresponds to respective ones of said binary digits.