Teaching machine

• US 3,999,307 A
• Filed: 08/06/1971
• Issued: 12/28/1976
• Est. Priority Date: 08/07/1970
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Tsuda, Junji, Hirano, Chiakafusa
• Primary Examiner(s): Pinkham, Richard C.
• Assistant Examiner(s): Hum, Vance Y.
• Application Number:
  US05/169,614
• Time in Patent Office: 1,971 Days
• Field of Search: 35/6, 35/9 A, 35/9 R, 35/31 C, 35/35 C, 35/48 R, 35/8 R, 35/8 A
• US Class Current: 434/323
• CPC Class Codes: G09B 7/04 characterised by modifying the teaching programme in response to a wrong answer, e.g. repeating the question, supplying a further explanation

Abstract

An instructional device in the form of a special purpose computer comprising a display device for displaying teaching materials and other information, a keyboard for the student to make a response to the given information, and a control circuit; wherein said control circuit decodes in sequence the orders supplied in the form of program, provides the student with necessary teaching materials, reads the response from the student, judges the read response, and determines the program to be executed in the next place according to the judged result. This instructional device makes a great teaching freedom available to meet the individual abilities of the students.

Claims

1. An instructional apparatus comprising a plurality of student stations and a program-feeding device for storing and supplying programmed data to be used by a student wherein each said student station comprises:

display means for displaying data for the use of said student;

input means for enabling the student to write information into a random access memory in response to data displayed on said display means;

a random access memory for storing the program supplied from the program-feeding device and storing various information produced as a result of program execution;

control means coupled to said display means, input means, program-feeding device and random access memory, including;

means for writing in only one step-program supplied from the program-feeding device at a predetermined location of said random access memory, said one step-program being comprised by a presentation order, a pause order, a judge order and a request order;

means, responsive to a presentation order, for supplying selected information to said display means to present questions to a student;

means, responsive to the pause order, for temporarily storing said information from the student at a predetermined location of said random access memory through his operation of said input means in response to the information displayed on said display means;

means, responsive to the judge order, for comparing said information from said student with expected response data and for evaluating and judging the result of said comparison; and

means, responsive to the request order, for designating a subsequent step-program to be executed and for delivering a request signal to said program-feeding device.

2. An instructional apparatus according to claim 1, in which said selected information supplying means comprises:

a first register, coupled to said random access memory, for storing a signal representative of an address within said memory;

a control signal generator circuit for generating a read signal for reading an instruction into the address designated by said first register;

a second register, coupled to said control signal generator circuit, for temporarily storing a code which designates the type of said read instruction;

a third register, coupled to said control signal generator circuit, for temporarily storing a code which designates a particular display means to be operated in response to said read instruction;

a counter, coupled to said control signal generator circuit, for temporarily storing a signal which designates the word length of data to be presented according to said read instruction;

means for supplying, from said control signal generator circuit to said first register, a signal for changing the contents of said first register, so that the contents of said first register indicate the next address each time one word is read from said memory;

means for supplying, from said control signal generator circuit to said counter, a signal for subtracting a specific value from the contents of said counter each time one word of the information read from said memory is sent to said designated display means; and

means for supplying, from said control signal generator circuit to said display means, a signal for instructing the designated display device to accept information according to the contents of said second and third registers.

3. An instructional apparatus according to claim 2, in which said input means includes a keyboard comprising

message keys for the student to input his answer or other information,

response keys for discriminating the type of student'"'"'s response and for indicating the end of a student'"'"'s response, and

a key for requesting the cancellation of input information.

4. An instructional apparatus according to claim 3, further including a first gate through which the output of said message key is applied to said control means, and a first flip-flop, responsive to said control signal generator circuit and being connected to said first gate and wherein said first gate is controlled by the output of said first flip-flop to be set by a signal from said selected information supplying means, when the student'"'"'s response is terminated.

5. An instructional apparatus according to claim 1, in which said temporarily storing means comprises:

a control signal generator circuit;

a memory buffer register for temporarily storing the output of said input means;

a fixed address generator for indicating the address of a predetermined region of said random access memory;

a first register for temporarily storing an indication from said fixed address generator;

means for supplying, from said control signal generator circuit to said random access memory, a write signal for writing in said memory the information stored in said memory buffer register; and

means for supplying, from said control signal generator circuit to said first register, a signal for changing the contents of said first register to the next address each time one word is written into said random access memory.

6. An instructional apparatus according to claim 5, in which said temporarily storing means further comprises

an end-code generator, and

a first gate, responsive to the output of said end-code generator, for supplying said memory buffer register with the output of said end-code generator at the end of the information supplied from said input means and

further including means for storing the end-code at the end of the student'"'"'s response in said random access memory.

7. An instructional apparatus according to claim 1, in which said comparing means comprises:

a control signal generator circuit;

an accumulator for storing information;

an adder circuit connected to said accumulator so that the output of said accumulator is applied to the summand side input terminal of said adder circuit, and the output of said adder circuit is applied to the input of said accumulator;

a first register to be set at the address of said random access memory in which numerical data is stored;

means for supplying, from said control signal generator circuit to said memory, a signal for reading information from the address indicated by said first register; and

means for applying the signal read from said memory to the addend side input terminal of said adder circuit.

8. An instructional apparaus according to claim 1, in which said comparing means comprises:

a control signal generator circuit;

an accumulator in which information to be stored in said memory is stored;

a first register in which the address to be stored is temporarily stored;

a memory buffer register;

a first gate, controlled so that the information in said accumulator is transferred to said memory buffer register by the signal from said control signal generator; and

means for supplying, from said control signal generator to said random access memory, a write signal for writing the information stored in said temporarily storing means into the address of said random access memory, which address is indicated by the contents of said first register.

9. An instructional apparatus according to claim 1, in which said comparing means comprises:

a first register in which an order code to be compared with a student'"'"'s response information is set;

a counter in which the information indicating the word length of information expected from said input means is set;

a second register in which the address of the first character of the expected information stored in said memory is stored;

a third register in which the first address of said student'"'"'s input information is stored;

an accumulator;

a control signal generator circuit;

means for supplying, from said control signal generator circuit to said memory, a read signal for reading information in the address indicated by said second register according to the state of said first register;

means for transferring said read signal to said accumulator;

means for supplying, from said control signal generator circuit to said second register, a signal for transferring the contents of said second register to the next address after said transfer of said read signal to said accumulator;

means for supplying, from said control signal generator circuit to said third register, a signal for reading the information in the address indicated by said third register;

means for applying a student'"'"'s input information to said accumulator through an inverter, which inverts the bit signals of said student'"'"'s input information;

a flip-flop, coupled to said control signal generator, which is set when the contents of said accumulator are not zero; and

means for supplying, from said control signalgenerator circuit to said counter, a signal for subtracting a specific value from the value of said counter each time the comparison of one character ends; and

means for effecting the repetition of the operation of said comparing means until the contents of said counter become zero.

10. An instructional apparatus according to claim 1, in which said comparing means comprises:

a plurality of flip-flops, set in response to information supplied from said input means;

a flip-flop set according to whether or not the student'"'"'s information response message is coincident with expected information;

a first register for storing an order code;

a second register for storing a code which designates one of said flip-flops of said plurality;

a memory buffer register for storing a code which indicates a specific address of said random access memory;

a control signal generator circuit, coupled to receive a set signal from the flip-flop designated by said second register when this flip-flop is in the set state;

a third register set according to an address of said memory; and

means for supplying, from said control signal generator circuit to a gate, a pulse for controlling said gate, so that the information in said memory buffer register is transferred to said third register when the designated flip-flop is delivering a set signal.

11. An instructional apparatus according to claim 1, inwhich said comparing means comprises:

a control signal generator circuit;

an accumulator in which arbitrary information can be stored;

a decision circuit for judging whether the contents of said accumulator are positive, zero or negative; and

means for supplying said control signal generator circuit with a signal corresponding to the judged result.

12. An instructional apparatus according to claim 1, in which said temporarily storing means comprising:

a buffer register for temporarily storing the result of a student'"'"'s response placed in said input means, by sequentially storing the student'"'"'s input information;

a plurality of flip-flops for storing information corresponding to the type of student'"'"'s responses;

a counter for counting the student'"'"'s response time; and

a first flip-flop for controlling application of information to said memory, said first flip-flop being set in response to the execution of a pause order permitting the entry of a student'"'"'s response, and wherein said first flip-flop is reset when one of the flip-flops of said plurality is set upon termination of the student'"'"'s response or when a second flip-flop, responsive to said counter, is set as the result that the student'"'"'s response time has elapsed, and thus the student'"'"'s response is allowed, and the result of student'"'"'s response is stored, the student'"'"'s response requiring time being counted only when said first flip-flop is in the set state.

13. An instructional apparatus according to claim 1, in which said program-feeding device includes means for continuously feeding individual programs based on a request order given once.

14. An instructional apparatus according to claim 1, wherein said apparatus further includes access to a computing means and in which said designating means comprises:

a first register for storing a signal which designates an address within said random access memory;

a control signal generator circuit which generates a signal for reading an order from the address designated by said first register;

a second register for temporarily storing a code which designates the type of read order;

a third register for temporarily storing a code which designates access to said computing means according to said read order;

a counter for temporarily storing a signal which designates the word length of information requested by said read order;

means for supplying, from said control signal generator circuit to said first register, a signal for changing the contents of said first register, so that the contents of said first register indicate the next address each time one word is read from said memory;

means for supplying, from said control signal generator circuit to said counter, a signal for subtracting a specific value from the contents of said counter each time one word of the information read from the memory is transmitted to said computing means; and

means for supplying from said control signal generator circuit a signal for enabling said computing means to accept said information according to the contents of said second and third registers.