Data array network system

• US 4,001,769 A
• Filed: 10/28/1975
• Issued: 01/04/1977
• Est. Priority Date: 03/28/1975
• Status: Expired due to Term

• Current Assignee: Geophysical Systems Corp.
• Original Assignee: Geophysical Systems Corp.
• Inventors: Westphal, James A., Fort, J. Robert, Juilfs, Donald R.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Rhoads, Jan E.
• Application Number:
  US05/626,139
• Time in Patent Office: 434 Days
• Field of Search: 445/1, 340/172.5, 340/155, 340/15.5 CD, 340/15.5 DA, 340/15.5 TS, 340/145 R, 340/147 SY, 346/33 C, 235/151.35, 178/58 R, 178/69.5 R, 179/15 AL
• US Class Current: 367/79
• CPC Class Codes: G01V 1/22 Transmitting seismic signals to recording or processing apparatus

Abstract

A system for the field recording of seismic data in which a large plurality of geophones are arrayed on the earth and divided into groups, and each group is connected to an array terminal. All of the array terminals are connected in series, by cables, with the last terminal connected to a recording unit. In each of the terminals there are means to process the geophone analog signals by amplifying at constant gain and digitizing to 1 bit to provide a plurality of 1 bit pulses, which are stored in parallel in a parallel to serial convertor. On command from the recording unit, the bits stored in the convertors are read out in series and are transmitted by a pair of signal conductors to the next in series terminal for storage in the convertor, and from there to the convertor in the next in series terminal, and so on, until all of the bits stored in each of the terminals are transmitted as a plurality of short trains of single bit signals, to the recording unit, where they are recorded on a magnetic digital storage means. Each of the array terminals has an address register in which an address is stored, which is transmitted as a heading to the data stored in that convertor.

Claims

1. A data gathering system comprising:

a. a plurality of array terminals, each having a parallel to serial convertor means;

b. each array terminal having a plurality of conductor means, each connected to at least one detector so that said detectors can be positioned in selected spaced relation, to sense at least one physical parameter, and to produce an analog signal indicative of said parameter;

c. each array terminal having an input port and an output port, into each of which a multiple conductor cable is connected, said multiple conductors comprising signal and control conductors;

d. means, including a plurality of selected lengths of said cable, to connect said array terminals in series connection, and to connect the last in series of said terminals to array controller means, said signal conductors connecting said parallel to serial convertor means in adjacent terminals;

e. means, in said array controller means, to signal said terminals, by a coded signal on said control conductors;

f. a plurality of means in each array terminal, each one in circuit with one of said detector means to amplify, digitize to 1 bit said analog signal, and to store said digitized signals in said parallel to serial convertor means;

g. means, on command from said array controller means, to read out and transmit said 1 bit digitized signals, stored in said convertor means, to the convertor means in the next in series array terminal,

whereby said digitized signals are transmitted sequentially through each of said convertor means to said array controller means.

2. A data acquisition system comprising:

a. a plurality of N spaced apart array terminals, and means for collecting a plurality of M analog signals into each of said terminals;

b. means, in each of said terminals, for converting said analog signals to digital signals and storing same in parallel to serial convertor means;

c. means to connect said parallel to serial convertor means in each of said terminals in series operative connection and to a data storage means in an array controller means; and

d. means, on command from said array controller to each of said array terminals, to sequentially transmit the stored digital data in each of said parallel to serial convertor means to and through each of the parallel to serial convertor means in each of the array terminals in series and to said array controller.

3. The system as in claim 2 in which said digital signal are 1 bit signals.

4. The system as in claim 3 including clock means to regenerate the clock timing from the incoming data from the next succeeding array terminal, to read said data into said convertor means, and to provide clock pulses to read data out of said convertor means and into the preceding in series array terminal.

5. A data acquisition system comprising:

a. at least three spaced apart array terminals, A, B, C where commands from an array controller are sent to A, then to B, then to C, and means for collecting at least one analog signal into each of said terminals;

b. means, in each of said terminals, for converting said analog signals to digital signals and storing same in a parallel to serial convertor means in said terminals;

c. first conductor means to connect said register means in said terminal B to register means in the preceding in series terminal A, and second conductor means to connect said register means in said terminal B to the succeeding in series terminal C;

d. clock means in each of said terminals, and means to transmit, on said first conductor means, data stored in said register means to the preceding in series terminal A, at the rate of said clock means in B; and

e. means to receive in B, data from the succeeding in series terminal C, means to determine the clock rate of said received data, and means to read said received data into said register means in B at the clock rate of said received data.

6. The system as in claim 5 including means in said preceding in series terminal A to receive said digital signals transmitted from said terminal B, means to determine the clock rate of said received digital signals, and means to store said digital signals in register means in said terminal A at the clock rate of said received digital signals.

7. The system as in claim 5 in which said digital signals are single bit signals.

8. The system as in claim 5 in which said means to convert comprises:

a. means to amplify said analog signals at constant gain and convert to square waves signals;

b. means to transmit said square wave signals to said parallel to serial convertor means through gate means; and

c. means to momentarily open said gate means at selected times.

9. In a digital data acquisition system in which at least one analog signal is received in each of a plurality of signal terminals, clock means in each of terminals;

means in each of said terminals to convert said analog signals to digital signals and for storing said signals;

the improvement comprising;

a. multiple conductor means connecting said terminals in series and to a data storage and control means;

b. said multiple conductor means including;

1. at least two first conductors for digital data signal transmission; and

2. at least two second conductors for transmission of command signals from an array controller;

c. means in each terminal to transmit digital data signals over said first conductors in a first direction, to the preceding in series terminal; and

d. means in each terminal to transmit command signals over said second conductors in a second reverse direction from each terminal to the succeeding in series terminal.

10. The system as in claim 9 including means in each terminal on receipt of a command signal from said array controller to compare the address in said command signal with the address of said terminal, and including means to transmit said command to the next array terminal if said addresses are not the same.

11. The system as in claim 9 including means in each terminal, on receipt of a command signal from said array controller, to compare the address in said command signal with the address of said terminal, and including means to transmit said command signal with its address incremented by one to the next array terminal, if said addresses are the same.

12. The system as in claim 9 including means in each terminal, on receipt of a command signal from said control means to compare the address in said command signal with the address of said terminal, and if said addresses are the same, including means to initiate the transmission of the data stored in said parallel to serial convertor to the preceding in series terminal.

13. The system as in claim 9 including in each terminal address register means for holding a digital signal representing the address of said terminal, and including second register means in series with a parallel to serial convertor means, and means for loading the address from said address register to said address serial register, and on command to transmit said digital data signals,

whereby said address forms a header for said digital data signals.

14. The system as in claim 9 including means in each terminal to transmit to the succeeding in series terminal a busy signal whenever said data register means contains data.

15. In a data acquisition system comprising at least two array terminals (AT), each receiving a plurality of analog signals, means in each array terminal to

amplify at constant gain said analog signals,

digitize said amplified analog signals to 1 bit,

store said 1 bit digitized signals, in parallel, in parallel to serial convertor means,

clock means, and

means to determine clock rate from a train of digital 1 bit signals;

first conductor means to connect the convertor means in each AT to the convertor means in the adjacent terminals;

the method of acquisition and transport of said 1 bit signals, comprising;

a. on receipt of a selected command, addressed to a selected array terminal, amplifying, digitizing to 1 bit, and storing said analog signals in said parallel to serial convertor means;

b. transmitting, as a first serial train of 1 bit signals to the preceding in series array terminal over said first conductor means, at the clock rate of said clock means, the 1 bit signals stored in said convertor means;

c. receiving, from the succeeding in series AT over said first conductor means, a second train of 1 bit digital signals;

d. determining the clock rate of said second train of 1 bit digital signals; and

e. shifting said second train of 1 bit signals into said convertor means at the clock rate determined from said second train.

16. The method as in claim 15 including the additional steps between steps (a) and (b) of;

entering into an address register in series with said convertor means the address of said array terminal;

whereby in step (b) when said first train of 1 bit signals is shifted out of said convertor means, it will be shifted through said address register; and

said address stored in said address register will be transmitted to the next array terminal as a header to said train of 1 bit signals.

17. The method as in claim 15 including the additional steps comprising, on receipt of said commands;

comparing the address of said command to the address of said terminal and incrementing the address by one count and transmitting the incremented address to the next array terminal if said address are the same.

18. The method as in claim 15 including the additional steps comprising:

comparing the address of said command to the address of said terminal, and transmitting said address and command without change to the next array terminal if the addresses are not the same.