Full range correlator for use in a collision avoidance system

• US 4,003,050 A
• Filed: 04/21/1975
• Issued: 01/11/1977
• Est. Priority Date: 04/23/1974
• Status: Expired due to Term

• Current Assignee: RCA Corporation
• Original Assignee: RCA Corporation
• Inventors: Miller, Jeffrey Ellis
• Primary Examiner(s): Farley, Richard A.
• Assistant Examiner(s): Buczinski, S. C.
• Application Number:
  US05/569,995
• Time in Patent Office: 631 Days
• Field of Search: 343/6.5 R, 343/6.5 LC, 343/7.3, 343/5 DP
• US Class Current: 342/29
• CPC Class Codes: G01S 13/933 of aircraft or spacecraft
• CPC Class Codes: Y10S 428/916 Fraud or tamper detecting

Abstract

In a cooperative collision avoidance system, the reply signals to interrogation probe signals are correlated by a digital circuit that processes all the reply signals identifying targets over non-targets or "fruit." The correlator is capable of detecting all targets in any desired range during a given correlation period.

Claims

1. A circuit for correlating reply signals generated by remote stations in response to probe signals from interrogated stations, said reply signals being adapted to be received in an environment wherein signals of a type different from said replay signals may be received by said circuit, comprising the combination of:

a. sequential storage means for storing a plurality of binary numbers includng accessing means for storing input numbers and retrieving output numbers;

b. control means responsive to said reply signals and to said different signals for producing a first control signal in response to a reply signal and a second control signal in response to a different signal;

c. adder means coupled to receive said output numbers and responsive to said first and second control signals for changing the value of said output numbers in response to said first and second control signals; and

d. comparator means responsive to said output numbers and a reference number corresponding to minimum range for producing an output signal when said output number is equal to said input reference number.

2. A circuit according to claim 1 wherein said sequential storage means includes a plurality of shift registers, each register having a plurality of stages including an input and output stage and each stage adapted to store a binary logic bit signal,

said registers being arranged so that corresponding stages of each of said registers is a storage stage for a respective bit of said binary number,

clock means for clocking said registers and for sequentially transferring to said adder means a binary number stored in the output storage positions,

the binary number in said adder means being transferred in response to said clock means to the corresponding input stages of said shift registers.

3. A circuit according to claim 2 wherein said comparator means includes probe counter means responsive to said probes for inhibiting said output signal upon counting a predetermined number of probes.

4. A circuit according to claim 3 including a shift register stage counter responsive to said clock means for counting the clocked stages of said shift registers and to inhibit further clocking of said shift registers after a predetermined clocking period.

5. A circuit according to claim 4 further including a shift register stage address memory means for enabling said output signal at the stage wherein said binary number is equal to said reference number.

6. In a cooperative collision avoidance system employing two distinctive type probe signals transmitted from an interrogation station, including remote stations having means to respond to said probe signals and to generate reply signals corresponding to the type of probe signal received,

a. means responsive to said reply signals for generating a binary number representing the number of replies received during a predetermined period, said period corresponding to a range from said interrogation station to said remote stations,

b. storage means for storing a plurality of said binary numbers,

whereby the range of each reply received in response to a predetermined corresponding probe is stored in said storage means, and

c. comparator means for comparing each of said binary numbers to a predetermined reference number corresponding to a minimum critical range and generating an output signal for each reply signal from a remote station having a range less than said critical range.