Semiconductor device with high voltage breakdown resistance

• US 4,003,072 A
• Filed: 11/01/1974
• Issued: 01/11/1977
• Est. Priority Date: 04/20/1972
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Matsushita, Takeshi, Hayashi, Hisao
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US05/520,115
• Time in Patent Office: 802 Days
• Field of Search: 357/13, 357/20, 357/21, 357/22, 357/48, 357/52, 357/53, 357/68, 357/38, 357/34
• US Class Current: 257/170
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1025 Channel region of field-effect devices

Abstract

A semiconductor device including a substrate of semiconductor material having charge carriers of one conductivity type and a main region of opposite conductivity type. A ring of said opposite conductivity type is disposed around the main region and an auxiliary region of said opposite conductivity type is disposed on the opposite surface of the substrate. The said rings and the said auxiliary region are spaced from the main region by distances that permit the depletion region of the main region to reach the ring and the auxiliary region when the main region is reversed biased with respect to the substrate.

Claims

1. A semiconductor device comprising:

a planar substrate of semiconductor material of one conductivity type having first and second surfaces on opposite sides thereof;

a first region of the opposite conductivity type on said first surface of said substrate forming a first pn junction therewith;

a first electrode mounted on said first region;

a second region of said opposite conductivity type on said first surface of said substrate forming a second pn junction therewith which surrounds said first pn junction in predetermined spaced relation;

a third region of said opposite conductivity type on the second surface of said substrate forming a third pn junction therewith which faces said first region in predetermined spaced relation therewith;

the periphery of said third region extending beyond that of said first region;

said second and third regions being free of electrical connection;

a potential source reverse biasing said first pn junction with a potential of such magnitude such that the depletion layer will extend from said first pn junction to said second and third pn junctions;

a second electrode mounted on said substrate and disposed on a region of said one conductivity type on said first surface of said substrate, and the distance between said second electrode and said first region being larger than the distance between said first and second regions;

said potential source connected to said first and second electrodes;

said first, second and third regions being arranged so that a depletion layer extends from the vicinity of said first pn junction and surrounds said second and third regions so as to increase the breakdown voltage, and

insulating layers covering said first and second surfaces.

2. A semiconductor device according to claim 1 including a fourth region of said one conductivity type formed in said first region of opposite conductivity type, and a third electrode connected to said fourth region.

3. A semiconductor device as in claim 1 which has a fourth region surrounded by the first region and a fifth region of said opposite conductivity type surrounding said second pn junction and first, second and third electrodes attached to said first, fourth and fifth regions.

4. A semiconductor device according to claim 1 including insulating layers coating said second and third regions.

5. A semiconductor device comprising

a planar substrate of semiconductor material of one conductivity type having first and second surfaces on opposite sides thereof;

a first region of the opposite conductivity type on said first surface of said substrate forming a first pn junction therewith;

a first electrode mounted on said first region;

a second region of said opposite conductivity type on said first surface of said substrate forming a second pn junction therewith which surrounds said first pn junction in predetermined spaced relation;

an embedded third region of said opposite conductivity type formed in said substrate between said second surface of said substrate and said first region and forming a third pn junction therewith which faces said first region in predetermined spaced relation therewith;

the periphery of said third region extending beyond that of said first region;

said second and third regions being free of electrical connection;

a potential source reverse biasing said first pn junction with a potential of such magnitude such that the depletion layer extends from said first pn junction to said second and third pn junctions;

and a second electrode mounted on said substrate and disposed on a region of said one conductivity type of said first surface of said substrate, and the distance between said second electrode and said first region being larger than the distance between said first and second regions;

said potential source connected to said first and second electrodes;

said first, second and third regions being arranged so that a depletion layer extends from the vicinity of said first pn junction and surrounds said second and third regions and so as to increase the breakdown voltage; and

insulation layers covering said first and second surfaces.

6. A semiconductor device according to claim 5 including a fourth region of said one conductivity type formed in said first region of opposite conductivity type, and a third electrode connected to said fourth region.

7. A semiconductor device according to claim 6 wherein a fifth region of said opposite conductivity type is formed in the second surface of said substrate and forms a pn junction therewith and said fifth region being free of electrodes and facing said first region.

8. A semiconductor device according to claim 7 wherein said embedded third region is generally cylindrical in shape and has an axis corresponding to the height of said cylinder extending parallel to said first and second surfaces.

9. A semiconductor device as in claim 5 which has a fourth region of said one conductivity type surrounded by said first region and a fifth region of said opposite conductivity type surrounding said second pn junction and first, second and third electrodes attached to said first, fourth and fifth regions.

10. A semiconductor device comprising:

a planar substrate of semiconductor material of one conductivity type having first and second surfaces on opposite sides thereof;

a first region of the opposite conductivity type on said first surface of said substrate forming a first pn junction therewith;

a first electrode mounted on said first region;

a second region of said opposite conductivity type on said first surface of said substrate forming a second pn junction therewith which surrounds said first pn junction in predetermined spaced relation;

a third region of said opposite conductivity type on the second surface of said substrate forming a third pn junction therewith which faces said first region in predetermined spaced relation therewith;

the periphery of said third region extending beyond that of said first region;

the surface of said first region which faces said third region being cupped shape;

said second and third regions being free of electrical connection;

a potential source reverse biasing said first pn junction with a potential of such magnitude such that the depletion layer extends from said first pn junction to said second and third pn junctions;

and a second electrode mounted on said substrate and disposed on a region of said one conductivity type on said first surface of said substrate, and the distance between said second electrode and said first region being larger than the distance between said first and second regions;

said potential source connected to said first and second electrodes;

said first, second and third regions being arranged so that a depletion layer extends from the vicinity of said first pn junction and surrounds said second and third regions and thus so as to increase the breakdown voltage; and

insulating layers covering said first and second surfaces.

11. A semiconductor device according to claim 10 including a fourth region of said one conductivity type formed in said first region of opposite conductivity type, and a third electrode connected to said fourth region.

12. A semiconductor device according to claim 10 including a fourth region surrounded by the first region and a fifth region of said opposite conductivity type surrounding said second pn junction and first, second and third electrodes attached to said first, fourth and fifth regions.